Datasheet > EDJ1108DBSE-DG-F

EDJ1108DBSE-DG-F

更新时间： 2024-02-03 17:08:34

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器
页数	文件大小	规格书
179页	2013K
描述
DRAM,

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技术参数
数据手册

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EDJ1108DBSE-DG-F 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.75
Base Number Matches：	1

EDJ1108DBSE-DG-F 数据手册

PRELIMINARY DATA SHEET

1G bits DDR3 SDRAM

EDJ1108DBSE (128M words × 8 bits)

EDJ1116DBSE (64M words × 16 bits)

Features

Specifications

• Density: 1G bits

• Organization

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

⎯ 16M words × 8 bits × 8 banks (EDJ1108DBSE)

⎯ 8M words × 16 bits × 8 banks (EDJ1116DBSE)

• Package

⎯ 78-ball FBGA (EDJ1108DBSE)

⎯ 96-ball FBGA (EDJ1116DBSE)

⎯ Lead-free (RoHS compliant) and Halogen-free

• Power supply: VDD, VDDQ = 1.5V 0.075V

• Data rate

⎯ 1600Mbps/1333Mbps/1066Mbps/800Mbps (max.)

• 1KB page size (EDJ1108DBSE)

⎯ Row address: A0 to A13

⎯ Column address: A0 to A9 (EDJ1108DBSE)

• 2KB page size (EDJ1116DBSE)

⎯ Row address: A0 to A12

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• On-Die Termination (ODT) for better signal quality

⎯ Synchronous ODT

⎯ Dynamic ODT

⎯ Asynchronous ODT

• Multi Purpose Register (MPR) for temperature read

out

⎯ Column address: A0 to A9

• Eight internal banks for concurrent operation

• Interface: SSTL_15

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

⎯ Sequential (8, 4 with BC)

⎯ Interleave (8, 4 with BC)

• ZQ calibration for DQ drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

• /CAS Write Latency (CWL): 5, 6, 7, 8

• /RESET pin for Power-up sequence and reset

function

• SRT range:

⎯ Normal/extended

• Precharge: auto precharge option for each burst

access

• Driver strength: RZQ/7, RZQ/6, RZQ/5 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

• Programmable Output driver impedance control

• Seamless BL4 access with bank-grouping

⎯ Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Operating case temperature range

⎯ TC = 0°C to +95°C

Document No. E1463E30 (Ver. 3.0)

Date Published July 2009 (K) Japan

Printed in Japan

URL: http://www.elpida.com

12 3 4 5 6 7...179

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与EDJ1108DBSE-DG-F相关器件

型号	品牌	描述	获取价格	数据表
EDJ1108DBSE-DJ-F	ELPIDA	DDR DRAM, 128MX8, 0.255ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	获取价格
EDJ1108DBSE-GL-F	ELPIDA	DRAM,	获取价格
EDJ1108DBSE-GN-F	ELPIDA	DDR DRAM, 128MX8, 0.225ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78	获取价格
EDJ1108DJBG	ELPIDA	Differential clock inputs	获取价格
EDJ1108DJBG-DJ-F	ELPIDA	Differential clock inputs	获取价格
EDJ1108DJBG-DN-F	ELPIDA	Differential clock inputs	获取价格

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