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EDI88512LPA-17RJMG PDF预览

EDI88512LPA-17RJMG

更新时间： 2024-11-03 08:49:15
品牌 Logo 应用领域
美高森美 - MICROSEMI 静态存储器光电二极管
页数 文件大小 规格书
9页 796K
描述
Standard SRAM, 512KX8, 17ns, CMOS, PDSO36, ROHS COMPLIANT, PLASTIC, REVOLUTIONARY, SOJ-36

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EDI88512LPA-17RJMG 数据手册

 浏览型号EDI88512LPA-17RJMG的Datasheet PDF文件第2页浏览型号EDI88512LPA-17RJMG的Datasheet PDF文件第3页浏览型号EDI88512LPA-17RJMG的Datasheet PDF文件第4页浏览型号EDI88512LPA-17RJMG的Datasheet PDF文件第5页浏览型号EDI88512LPA-17RJMG的Datasheet PDF文件第6页浏览型号EDI88512LPA-17RJMG的Datasheet PDF文件第7页 
EDI88512CA-XMXG  
WPS512K8X-XRJXG  
512Kx8 Plastic Monolithic SRAM CMOS  
WEDC's ruggedized plastic 512Kx8 SRAM that allows the user to  
capitalize on the cost advantage of using a plastic component while  
not sacrificing all of the reliability available in a full military device.  
FEATURES  
 512Kx8 bit CMOS Static  
 Random Access Memory  
Extended temperature testing is performed with the test patterns  
developed for use on WEDC’s fully compliant 512Kx8 SRAMs.  
WEDC fully characterizes devices to determine the proper test  
patterns for testing at temperature extremes. This is critical because  
the operating characteristics of device change when it is operated  
beyond the commercial guarantee a device that operates reliably  
in the field at temperature extremes. Users of WEDC’s ruggedized  
plastic benefit from WEDC’s extensive experience in characterizing  
SRAMs for use in military systems.  
• Access Times of 17, 20, 25ns  
• Data Retention Function (LPA version)  
• Extended Temperature Testing  
• Data Retention Functionality Testing  
 36 lead JEDEC Approved Revolutionary Pinout  
• Plastic SOJ (Package 319)  
 Single +5V (±10%) Supply Operation  
 RoHS compliant  
WEDC ensures Low Power devices will retain data in Data  
Retention mode by characterizing the devices to determine the  
appropriate test conditions. This is crucial for systems operating  
at -40°C or below and using dense memories such as 512Kx8s.  
WEDC’s ruggedized plastic SOJ is footprint compatible with  
WEDC’s full military ceramic 36 pin SOJ.  
FIGURE 1 – PIN CONFIGURATION  
TOP VIEW  
PIN Description  
I/O0-7  
A0-18  
WE#  
CS#  
OE#  
VCC  
Data Inputs/Outputs  
Address Inputs  
Write Enables  
Chip Selects  
A0  
A1  
1
2
3
4
5
6
7
8
9
36 NC  
35 A18  
34 A17  
33 A16  
32 A15  
31 OE#  
30 I/O7  
29 I/O6  
28 VSS  
27 VCC  
26 I/O5  
25 I/O4  
24 A14  
23 A13  
22 A12  
21 A11  
20 A10  
19 NC  
Output Enable  
Power (+5V ±10%)  
Ground  
A2  
A3  
VSS  
A4  
NC  
Not Connected  
CS#  
I/O0  
I/O1  
VCC  
BLOCK DIAGRAM  
36pin  
VSS 10  
I/O2 11  
I/O3 12  
WE# 13  
A5 14  
Revolutionary  
Memory Array  
A6 15  
A7 16  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
AØ-18  
I/OØ-7  
A8 17  
A9 18  
WE#  
CS#  
OE#  
Microsemi Corporation reserves the right to change products or specifications without notice.  
February 2011 © 2011 Microsemi Corporation. All rights reserved.  
Rev. 10  
1
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com  
www.microsemi.com  
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