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EDI88512CA35CB

更新时间： 2024-11-01 20:29:39
品牌 Logo 应用领域
玛居礼 - MERCURY 输入元件静态存储器输出元件内存集成电路
页数 文件大小 规格书
10页 1121K
描述
Standard SRAM, 512KX8, 35ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

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EDI88512CA35CB 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.32.00.41风险等级：5.57
Is Samacsys：NBase Number Matches：1

EDI88512CA35CB 数据手册

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EDI88512CA  
512Kx8 Monolithic SRAM, SMD 5962-95600  
FEATURES  
 Access Times of 15, 17, 20, 25, 35, 45, 55ns  
 Data Retention Function (LPA version)  
 TTL Compatible Inputs and Outputs  
 Fully Static, No Clocks  
The EDI88512CA is a 4 megabit Monolithic CMOS Static RAM.  
The 32 pin DIP pinout adheres to the JEDEC evolutionary standard  
for the four megabit device. All 32 pin packages are pin for pin  
upgrades for the single chip enable 128K x 8, the EDI88128CS.  
Pins 1 and 30 become the higher order addresses.  
 Organized as 512Kx8  
The 36 pin revolutionary pinout also adheres to the JEDEC  
standard for the four megabit device. The center pin power and  
ground pins help to reduce noise in high performance systems.  
The 36 pin pinout also allows the user an upgrade path to the  
future 2Mx8.  
 Commercial, Industrial and Military Temperature Ranges  
 32 lead JEDEC Approved Evolutionary Pinout  
• Ceramic Sidebrazed 600 mil DIP (Package 9)  
• Ceramic Sidebrazed 400 mil DIP (Package 326)  
• Ceramic 32 pin Flatpack (Package 344)  
• Ceramic Thin Flatpack (Package 321)  
• Ceramic SOJ (Package 140)  
A Low Power version with Data Retention (EDI88512LPA) is  
also available for battery backed applications. Military product is  
available compliant to Appendix A of MIL-PRF-38535.  
 36 lead JEDEC Approved Revolutionary Pinout  
• Ceramic Flatpack (Package 316)  
*This product is subject to change without notice.  
• Ceramic SOJ (Package 327)  
• Ceramic LCC (Package 502)  
 Single +5V (±10%) Supply Operation  
FIGURE 1 – PIN CONFIGURATION  
PIN DESCRIPTION  
Data Inputs/Outputs  
Address Inputs  
Write Enables  
Chip Selects  
I/O0-7  
A0-18  
WE#  
CS#  
OE#  
VCC  
VSS  
Output Enable  
Power (+5V ±10%)  
Ground  
36 PIN  
32 PIN  
TOP VIEW  
TOP VIEW  
NC  
Not Connected  
1
2
36 NC  
35 A18  
34 A17  
33 A16  
32 A15  
31 OE#  
30 I/O7  
29 I/O6  
32 Vcc  
31 A15  
30 A17  
29 WE#  
28 A13  
27 A8  
A0  
A1  
A18  
A16  
A14  
A12  
A7  
1
2
3
A2  
3
4
A3  
4
BLOCK DIAGRAM  
5
A4  
5
6
CS#  
I/O0  
I/O1  
Vcc  
Vss  
I/O2  
I/O3  
WE#  
A5  
A6  
6
26 A9  
7
A5  
7
32 pin  
Evolutionary  
25 A11  
24 OE#  
23 A10  
22 CS#  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
8
8
A4  
36 pin  
Revolutionary  
Memory Array  
9
Vss  
Vcc  
I/O5  
I/O4  
A14  
A13  
A12  
A11  
A10  
NC  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
9
A3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
10  
11  
12  
13  
14  
A2  
A1  
A0  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
0-18  
I/O0-7  
I/O0  
I/O1  
A6  
I/O2 15  
A7  
Vss  
16  
WE#  
CS#  
OE#  
A8  
A9  
Microsemi Corporation reserves the right to change products or specifications without notice.  
May 2014 © 2014 Microsemi Corporation. All rights reserved.  
Rev. 15  
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp  
1234567...10

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