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EDI88130LPS55LM PDF预览

EDI88130LPS55LM

更新时间: 2024-11-03 04:43:07
品牌 Logo 应用领域
美高森美 - MICROSEMI 静态存储器内存集成电路
页数 文件大小 规格书
10页 1086K
描述
Standard SRAM, 128KX8, 55ns, CMOS, CDSO32, CERAMIC, LCC-32

EDI88130LPS55LM 技术参数

是否Rohs认证: 不符合生命周期:Transferred
零件包装代码:DLCC包装说明:SON, SOLCC32,.4
针数:32Reach Compliance Code:unknown
风险等级:5.88最长访问时间:55 ns
I/O 类型:COMMONJESD-30 代码:R-XDSO-N32
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8端子数量:32
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:128KX8
输出特性:3-STATE封装主体材料:CERAMIC
封装代码:SON封装等效代码:SOLCC32,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified最大待机电流:0.002 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.2 mA标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL

EDI88130LPS55LM 数据手册

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EDI88130CS  
128Kx8 Monolithic SRAM, SMD 5962-89598  
FEATURES  
 Access Times of 15*, 17, 20, 25, 35, 45, 55ns  
An additional chip enable line provides system memory security  
during power down in non-battery backed up systems and memory  
banking in high speed battery backed systems where large multiple  
pages of memory are required.  
 Battery Back-up Operation  
• 2V Data Retention (EDI88130LPS)  
 CS1#, CS2 & OE# Functions for Bus Control  
 Inputs and Outputs Directly TTL Compatible  
 Organized as 128Kx8  
The EDI88130CS has eight bi-directional input-output lines to provide  
simultaneous access to all bits in a word.  
A low power version, EDI88130LPS, offers a 2V data retention  
function for battery back-up applications.  
 Commercial, Industrial and Military Temperature Ranges  
 Thru-hole and Surface Mount Packages JEDEC Pinout  
• 32 pin Sidebrazed Ceramic DIP, 400 mil (Package 102)  
• 32 pin Sidebrazed Ceramic DIP, 600 mil (Package 9)  
• 32 lead Ceramic SOJ (Package 140)  
Military product is available compliant to MIL-PRF-38535.  
* 15ns access time is advanced information, contact factory for availability.  
This product is subject to change without notice.  
• 32 pad Ceramic Quad LCC (Package 12)  
• 32 pad Ceramic LCC (Package 141)  
• 32 lead Ceramic Flatpack (Package 142)  
 Single +5V (±10%) Supply OperationThe EDI88130CS is  
a high speed, high performance, 128Kx8 bits monolithic  
Static RAM.  
FIGURE 1 – PIN CONFIGURATION  
32 DIP  
32 SOJ  
32 QUAD LCC  
TOP VIEW  
PIN DESCRIPTION  
32 CLCC  
I/O0-7  
A0-16  
WE#  
Data Input/Output  
Address Inputs  
Write Enable  
Chip Select  
32 FLATPACK  
CS1#, CS2  
OE#  
TOP VIEW  
4
3
2
1
32  
31 30  
Output Enable  
Power Supply  
Ground  
5
6
29  
28  
27  
26  
25  
24  
23  
22  
21  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
I/O0  
WE#  
A13  
A8  
VCC  
NC  
A16  
A14  
A12  
A7  
1
2
3
4
5
6
7
8
9
32 VCC  
31 A15  
30 CS2#  
29 WE#  
28 A13  
27 A8  
VSS  
7
8
NC  
Not Connected  
A9  
9
A11  
OE#  
A10  
CS1#  
I/O7  
A6  
10  
11  
12  
13  
A5  
26 A9  
A4  
25 A11  
24 OE#  
23 A10  
22 CS1#  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
Block Diagram  
A3  
A2 10  
A1 11  
Memory Array  
14  
15  
16  
17 18  
19  
20  
A0 12  
I/O0 13  
I/O1 14  
I/O2 15  
VSS 16  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A0-16  
I/O0-7  
WE#  
CS1#  
CS2  
OE#  
Microsemi Corporation reserves the right to change products or specications without notice.  
October 2011 © 2011 Microsemi Corporation. All rights reserved.  
Rev. 13  
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com  

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