EDE5108AJBG-6E-E

更新时间： 2024-11-08 03:33:27

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
77页	621K
描述
512M bits DDR2 SDRAM

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中文翻译

获取价格

数据手册

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EDE5108AJBG-6E-E 数据手册

PRELIMINARY DATA SHEET

512M bits DDR2 SDRAM

EDE5108AJBG (64M words × 8 bits)

EDE5116AJBG (32M words × 16 bits)

Features

Specifications

• Density: 512M bits

• Organization

⎯ 16M words × 8 bits × 4 banks (EDE5108AJBG)

⎯ 8M words × 16 bits × 4 banks (EDE5116AJBG)

• Package

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

⎯ 60-ball FBGA (EDE5108AJBG)

⎯ 84-ball FBGA (EDE5116AJBG)

⎯ Lead-free (RoHS compliant)

• Power supply: VDD, VDDQ = 1.8V 0.1V

• Data rate: 800Mbps/667Mbps (max.)

• 1KB page size (EDE5108AJBG)

⎯ Row address: A0 to A13

⎯ Column address: A0 to A9

• 2KB page size (EDE5116AJBG)

⎯ Row address: A0 to A12

⎯ Column address: A0 to A9

• Four internal banks for concurrent operation

• Interface: SSTL_18

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• Programmable RDQS, /RDQS output for making × 8

organization compatible to × 4 organization

• Burst lengths (BL): 4, 8

• Burst type (BT):

⎯ Sequential (4, 8)

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation

⎯ Interleave (4, 8)

• /CAS Latency (CL): 3, 4, 5, 6

• Precharge: auto precharge option for each burst

access

• Driver strength: normal/weak

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

⎯ Average refresh period

7.8μs at 0°C ≤ TC ≤ +85°C

3.9μs at +85°C < TC ≤ +95°C

• Operating case temperature range

⎯ TC = 0°C to +95°C

Document No. E1044E20 (Ver. 2.0)

Date Published May 2007 (K) Japan

Printed in Japan

URL: http://www.elpida.com

12 3 4 5 6 7...77

中文翻译

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与EDE5108AJBG-6E-E相关器件

型号	品牌	获取价格	描述	数据表
EDE5108AJBG-8E-E	ELPIDA	获取价格	512M bits DDR2 SDRAM
EDE5108AJSE	ELPIDA	获取价格	512M bits DDR2 SDRAM
EDE5108AJSE-6E-E	ELPIDA	获取价格	512M bits DDR2 SDRAM
EDE5108AJSE-8E-E	ELPIDA	获取价格	512M bits DDR2 SDRAM
EDE5108AJSE-8G-E	ELPIDA	获取价格	DDR DRAM, 64MX8, 0.4ns, CMOS, PBGA60, ROHS COMPLIANT, FBGA-60
EDE5108GASA	ELPIDA	获取价格	512M bits DDR-II SDRAM
EDE5108GASA-4A-E	ELPIDA	获取价格	512M bits DDR-II SDRAM
EDE5108GASA-5A-E	ELPIDA	获取价格	512M bits DDR-II SDRAM
EDE5108GBSA	ELPIDA	获取价格	512M bits DDR-II SDRAM
EDE5108GBSA-4A-E	ELPIDA	获取价格	512M bits DDR-II SDRAM

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