Datasheet > 存储 > DRAM> EDE2516AEBG

EDE2516AEBG

更新时间： 2024-09-18 06:55:55

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
77页	616K
描述
256M bits DDR2 SDRAM

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EDE2516AEBG 数据手册

DATA SHEET

256M bits DDR2 SDRAM

EDE2508AEBG (32M words × 8 bits)

EDE2516AEBG (16M words × 16 bits)

Features

Specifications

• Density: 256M bits

• Organization

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

⎯ 8M words × 8 bits × 4 banks (EDE2508AEBG)

⎯ 4M words × 16 bits × 4 banks (EDE2516AEBG)

• Package

⎯ 60-ball FBGA (EDE2508AEBG)

⎯ 84-ball FBGA (EDE2516AEBG)

⎯ Lead-free (RoHS compliant)

• Power supply: VDD, VDDQ = 1.8V 0.1V

• Data rate: 800Mbps/667Mbps (max.)

• 1KB page size

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

⎯ Row address: A0 to A12

⎯ Column address: A0 to A9 (EDE2508AEBG)

• Data mask (DM) for write data

A0 to A8 (EDE2516AEBG)

• Posted /CAS by programmable additive latency for

• Four internal banks for concurrent operation

• Interface: SSTL_18

• Burst lengths (BL): 4, 8

• Burst type (BT):

⎯ Sequential (4, 8)

⎯ Interleave (4, 8)

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• Programmable RDQS, /RDQS output for making × 8

organization compatible to × 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation

• /CAS Latency (CL): 3, 4, 5, 6

• Precharge: auto precharge option for each burst

access

• Driver strength: normal/weak

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

⎯ Average refresh period

7.8μs at 0°C ≤ TC ≤ +85°C

3.9μs at +85°C < TC ≤ +95°C

• Operating case temperature range

⎯ TC = 0°C to +95°C

Document No. E1175E20 (Ver. 2.0)

Date Published January 2008 (K) Japan

Printed in Japan

URL: http://www.elpida.com

©Elpida Memory, Inc. 2007-2008

12 3 4 5 6 7...77

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与EDE2516AEBG相关器件

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EDE2516AEBG-1J-E	ELPIDA	获取价格	DDR DRAM, 16MX16, 0.35ns, CMOS, PBGA84, ROHS COMPLIANT, FBGA-84
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EDE2516AEBG-8E-E	ELPIDA	获取价格	256M bits DDR2 SDRAM
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EDE5104ABSA-5A-E	ELPIDA	获取价格	DDR DRAM, 128MX4, 0.5ns, CMOS, PBGA64, MICRO, FBGA-64
EDE5104ABSE	ELPIDA	获取价格	512M bits DDR2 SDRAM
EDE5104ABSE-4A-E	ELPIDA	获取价格	512M bits DDR2 SDRAM
EDE5104ABSE-5A-E	ELPIDA	获取价格	DDR DRAM, 128MX4, 0.5ns, CMOS, PBGA64, MICRO, FBGA-64
EDE5104ABSE-5C-E	ELPIDA	获取价格	512M bits DDR2 SDRAM