Datasheet > EDE2104ABSE-5C-E

EDE2104ABSE-5C-E

更新时间： 2024-11-07 03:22:39

品牌	Logo	应用领域
尔必达 - ELPIDA		内存集成电路动态存储器双倍数据速率时钟
页数	文件大小	规格书
81页	630K
描述
2G bits DDR2 SDRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EDE2104ABSE-5C-E 数据手册

PRELIMINARY DATA SHEET

2G bits DDR2 SDRAM

EDE2104ABSE (512M words × 4 bits)

EDE2108ABSE (256M words × 8 bits)

Features

Specifications

• Density: 2G bits

• Organization

⎯ 64M words × 4 bits × 8 banks (EDE2104ABSE)

⎯ 32M words × 8 bits × 8 banks (EDE2108ABSE)

• Package

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

⎯ 68-ball FBGA

⎯ Lead-free (RoHS compliant)

• Power supply: VDD, VDDQ = 1.8V 0.1V

• Data rate

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

⎯ 800Mbps/667Mbps/533Mbps (max.)

• 1KB page size

⎯ Row address: A0 to A14

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

⎯ Column address: A0 to A9, A11 (EDE2104ABSE)

• Data mask (DM) for write data

A0 to A9 (EDE2108ABSE)

• Posted /CAS by programmable additive latency for

• Eight internal banks for concurrent operation

• Interface: SSTL_18

• Burst lengths (BL): 4, 8

• Burst type (BT):

⎯ Sequential (4, 8)

⎯ Interleave (4, 8)

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• Programmable RDQS, /RDQS output for making × 8

organization compatible to × 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation

• /CAS Latency (CL): 3, 4, 5, 6

• Precharge: auto precharge option for each burst

access

• Driver strength: normal/weak

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

⎯ Average refresh period

7.8μs at 0°C ≤ TC ≤ +85°C

3.9μs at +85°C < TC ≤ +95°C

• Operating case temperature range

⎯ TC = 0°C to +95°C

Document No. E1196E10 (Ver. 1.0)

Date Published November 2007 (K) Japan

Printed in Japan

URL: http://www.elpida.com

©Elpida Memory, Inc. 2007

12 3 4 5 6 7...81

中文翻译

下载PDF

与EDE2104ABSE-5C-E相关器件

型号	品牌	获取价格	描述	数据表
EDE2104ABSE-6E-E	ELPIDA	获取价格	2G bits DDR2 SDRAM
EDE2104ABSE-8G-E	ELPIDA	获取价格	2G bits DDR2 SDRAM
EDE2108AASE-6E-E	ELPIDA	获取价格	DDR DRAM, 256MX8, CMOS, PBGA68, ROHS COMPLIANT, FBGA-68
EDE2108AASE-8G-E	ELPIDA	获取价格	DDR DRAM, 256MX8, CMOS, PBGA68, ROHS COMPLIANT, FBGA-68
EDE2108ABSE	ELPIDA	获取价格	2G bits DDR2 SDRAM
EDE2108ABSE-5C-E	ELPIDA	获取价格	2G bits DDR2 SDRAM
EDE2108ABSE-6E-E	ELPIDA	获取价格	2G bits DDR2 SDRAM
EDE2108ABSE-8G-E	ELPIDA	获取价格	2G bits DDR2 SDRAM
EDE2108AEBG	ELPIDA	获取价格	Lead-free (RoHS compliant) and Halogen-free
EDE2108AEBG-8E-F	ELPIDA	获取价格	Lead-free (RoHS compliant) and Halogen-free