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EDE1116BEBG PDF预览

EDE1116BEBG

更新时间: 2024-09-18 11:45:07
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
77页 765K
描述
1G bits DDR2 SDRAM

EDE1116BEBG 数据手册

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PRELIMINARY DATA SHEET  
1G bits DDR2 SDRAM  
EDE1116BEBG (64M words × 16 bits)  
Specifications  
Features  
Density: 1G bits  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
8M words × 16 bits × 8 banks  
Package  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
84-ball FBGA  
Lead-free (RoHS compliant) and Halogen-free  
Power supply: VDD, VDDQ = 1.5V ± 0.075V  
Data rate: 667Mbps (max.)  
2KB page size  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Row address: A0 to A12  
Column address: A0 to A9  
Eight internal banks for concurrent operation  
Interface: SSTL_18  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Data mask (DM) for write data  
Burst lengths (BL): 4, 8  
Burst type (BT):  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Sequential (4, 8)  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
Interleave (4, 8)  
/CAS Latency (CL): 3, 4, 5, 6  
/DQS can be disabled for single-ended Data Strobe  
operation  
Precharge: auto precharge option for each burst  
access  
Driver strength: normal/weak  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Operating case temperature range  
TC = 0°C to +95°C  
Document No. E1369E10 (Ver. 1.0)  
Date Published August 2008 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2008  

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