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EDE1116AJBG-8E-F PDF预览

EDE1116AJBG-8E-F

更新时间: 2024-09-18 11:45:07
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
75页 556K
描述
1G bits DDR2 SDRAM

EDE1116AJBG-8E-F 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA84,9X15,32
针数:84Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.79Is Samacsys:N
访问模式:MULTI BANK PAGE BURST最长访问时间:0.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):400 MHz
I/O 类型:COMMON交错的突发长度:4,8
JESD-30 代码:R-PBGA-B84JESD-609代码:e1
长度:12.5 mm内存密度:1073741824 bit
内存集成电路类型:DDR DRAM内存宽度:16
湿度敏感等级:3功能数量:1
端口数量:1端子数量:84
字数:67108864 words字数代码:64000000
工作模式:SYNCHRONOUS组织:64MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA84,9X15,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.8 V
认证状态:Not Qualified刷新周期:8192
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:4,8最大待机电流:0.01 A
子类别:DRAMs最大压摆率:0.17 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8 mmBase Number Matches:1

EDE1116AJBG-8E-F 数据手册

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DATA SHEET  
1G bits DDR2 SDRAM  
EDE1108AJBG (128M words × 8 bits)  
EDE1116AJBG (64M words × 16 bits)  
Features  
Specifications  
Density: 1G bits  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
16M words × 8 bits × 8 banks (EDE1108AJBG)  
8M words × 16 bits × 8 banks (EDE1116AJBG)  
Package  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
60-ball FBGA (EDE1108AJBG)  
84-ball FBGA (EDE1116AJBG)  
Lead-free (RoHS compliant) and Halogen-free  
Power supply: VDD, VDDQ = 1.8V ± 0.1V  
Data rate  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
800Mbps (max.)  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
1KB page size (EDE1108AJBG)  
Row address: A0 to A13  
Data mask (DM) for write data  
Column address: A0 to A9  
2KB page size (EDE1116AJBG)  
Row address: A0 to A12  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Programmable RDQS, /RDQS output for making × 8  
organization compatible to × 4 organization  
Column address: A0 to A9  
Eight internal banks for concurrent operation  
Interface: SSTL_18  
/DQS, (/RDQS) can be disabled for single-ended  
Data Strobe operation  
Burst lengths (BL): 4, 8  
Off-Chip Driver (OCD) impedance adjustment is not  
supported.  
Burst type (BT):  
Sequential (4, 8)  
Interleave (4, 8)  
/CAS Latency (CL): 3, 4, 5, 6  
Precharge: auto precharge option for each burst  
access  
Driver strength: normal, weak  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Operating case temperature range  
TC = 0°C to +95°C  
Document No. E1732E21 (Ver.2.1)  
Date Published September 2011 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2010-2011  

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