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EDE1116ACSE-6C-E PDF预览

EDE1116ACSE-6C-E

更新时间: 2024-11-09 20:57:51
品牌 Logo 应用领域
尔必达 - ELPIDA 时钟动态存储器内存集成电路
页数 文件大小 规格书
82页 646K
描述
Synchronous DRAM, 64MX16, 0.45ns, CMOS, PBGA84, ROHS COMPLIANT, FBGA-84

EDE1116ACSE-6C-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA60,9X11,32
针数:84Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.82访问模式:MULTI BANK PAGE BURST
最长访问时间:0.45 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):333 MHzI/O 类型:COMMON
交错的突发长度:4,8JESD-30 代码:R-PBGA-B84
长度:13 mm内存密度:1073741824 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:84字数:67108864 words
字数代码:64000000工作模式:SYNCHRONOUS
组织:64MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA60,9X11,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.8 V认证状态:Not Qualified
刷新周期:8192座面最大高度:1.2 mm
自我刷新:YES连续突发长度:4,8
最大待机电流:0.01 A子类别:DRAMs
最大压摆率:0.315 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:11 mmBase Number Matches:1

EDE1116ACSE-6C-E 数据手册

 浏览型号EDE1116ACSE-6C-E的Datasheet PDF文件第2页浏览型号EDE1116ACSE-6C-E的Datasheet PDF文件第3页浏览型号EDE1116ACSE-6C-E的Datasheet PDF文件第4页浏览型号EDE1116ACSE-6C-E的Datasheet PDF文件第5页浏览型号EDE1116ACSE-6C-E的Datasheet PDF文件第6页浏览型号EDE1116ACSE-6C-E的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
1G bits DDR2 SDRAM  
EDE1104ACSE (256M words × 4 bits)  
EDE1108ACSE (128M words × 8 bits)  
EDE1116ACSE (64M words × 16 bits)  
Features  
Specifications  
Density: 1G bits  
Organization  
32M words × 4 bits × 8 banks (EDE1104ACSE)  
16M words × 8 bits × 8 banks (EDE1108ACSE)  
8M words × 16 bits × 8 banks (EDE1116ACSE)  
Package  
Double-data-rate architecture; two data transfers per  
clock cycle  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
60-ball FBGA (EDE1104/1108ACSE)  
84-ball FBGA (EDE1116ACSE)  
Lead-free (RoHS compliant)  
Power supply: VDD, VDDQ = 1.8V 0.1V  
Data rate  
800Mbps/667Mbps/533Mbps (max.)  
1KB page size (EDE1104/1108ACSE)  
Row address: A0 to A13  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Data mask (DM) for write data  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Column address: A0 to A9, A11 (EDE1104ACSE)  
A0 to A9 (EDE1108ACSE)  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
2KB page size (EDE1116ACSE)  
Row address: A0 to A12  
Column address: A0 to A9  
Eight internal banks for concurrent operation  
Interface: SSTL_18  
Programmable RDQS, /RDQS output for making × 8  
organization compatible to × 4 organization  
/DQS, (/RDQS) can be disabled for single-ended  
Data Strobe operation  
Burst lengths (BL): 4, 8  
Burst type (BT):  
Sequential (4, 8)  
Interleave (4, 8)  
/CAS Latency (CL): 3, 4, 5  
Precharge: auto precharge option for each burst  
access  
Driver strength: normal/weak  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period  
7.8μs at 0°C TC ≤ +85°C  
3.9μs at +85°C < TC ≤ +95°C  
Operating case temperature range  
TC = 0°C to +95°C  
Document No. E0975E20 (Ver. 2.0)  
Date Published January 2007 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
©Elpida Memory, Inc. 2006-2007  

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