Datasheet > EDE1116ABSE

EDE1116ABSE

更新时间： 2024-11-07 03:33:27

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
82页	645K
描述
1G bits DDR2 SDRAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EDE1116ABSE 数据手册

DATA SHEET

1G bits DDR2 SDRAM

EDE1104ABSE (256M words × 4 bits)

EDE1108ABSE (128M words × 8 bits)

EDE1116ABSE (64M words × 16 bits)

Features

Specifications

• Density: 1G bits

• Organization

⎯ 32M words × 4 bits × 8 banks (EDE1104ABSE)

⎯ 16M words × 8 bits × 8 banks (EDE1108ABSE)

⎯ 8M words × 16 bits × 8 banks (EDE1116ABSE)

• Package

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

⎯ 68-ball FBGA (EDE1104/1108ABSE)

⎯ 92-ball FBGA (EDE1116ABSE)

⎯ Lead-free (RoHS compliant)

• Power supply: VDD, VDDQ = 1.8V 0.1V

• Data rate

⎯ 800Mbps/667Mbps/533Mbps/400Mbps (max.)

• 1KB page size (EDE1104/1108ABSE)

⎯ Row address: A0 to A13

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

⎯ Column address: A0 to A9, A11 (EDE1104ABSE)

A0 to A9 (EDE1108ABSE)

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• 2KB page size (EDE1116ABSE)

⎯ Row address: A0 to A12

⎯ Column address: A0 to A9

• Eight internal banks for concurrent operation

• Interface: SSTL_18

• Programmable RDQS, /RDQS output for making × 8

organization compatible to × 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation

• Burst lengths (BL): 4, 8

• Burst type (BT):

⎯ Sequential (4, 8)

⎯ Interleave (4, 8)

• /CAS Latency (CL): 3, 4, 5

• Precharge: auto precharge option for each burst

access

• Driver strength: normal/weak

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

⎯ Average refresh period

7.8μs at 0°C ≤ TC ≤ +85°C

3.9μs at +85°C < TC ≤ +95°C

• Operating case temperature range

⎯ TC = 0°C to +95°C

Document No. E0852E50 (Ver. 5.0)

Date Published February 2007 (K) Japan

Printed in Japan

URL: http://www.elpida.com

12 3 4 5 6 7...82

中文翻译

下载PDF

与EDE1116ABSE相关器件

型号	品牌	获取价格	描述	数据表
EDE1116ABSE-4A-E	ELPIDA	获取价格	1G bits DDR2 SDRAM
EDE1116ABSE-5C-E	ELPIDA	获取价格	1G bits DDR2 SDRAM
EDE1116ABSE-6E-E	ELPIDA	获取价格	1G bits DDR2 SDRAM
EDE1116ACBG	ELPIDA	获取价格	1G bits DDR2 SDRAM
EDE1116ACBG-5C-E	ELPIDA	获取价格	1G bits DDR2 SDRAM
EDE1116ACBG-6E-E	ELPIDA	获取价格	1G bits DDR2 SDRAM
EDE1116ACBG-8E-E	ELPIDA	获取价格	1G bits DDR2 SDRAM
EDE1116ACSE	ELPIDA	获取价格	1G bits DDR2 SDRAM
EDE1116ACSE-5C-E	ELPIDA	获取价格	1G bits DDR2 SDRAM
EDE1116ACSE-6C-E	ELPIDA	获取价格	Synchronous DRAM, 64MX16, 0.45ns, CMOS, PBGA84, ROHS COMPLIANT, FBGA-84

与EDE1116ABSE相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

19
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

16
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

39
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

37

产品中心

服务支持

精选活动

关于我们

帮助中心

EDE1116ABSE

EDE1116ABSE 数据手册

与EDE1116ABSE相关器件

与EDE1116ABSE相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

EDE1116ABSE

EDE1116ABSE 数据手册

与EDE1116ABSE相关器件

与EDE1116ABSE相关文章

您还可以找

您在本页遇到什么问题？