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EDE1108AASE-5C-E PDF预览

EDE1108AASE-5C-E

更新时间: 2024-11-06 21:55:23
品牌 Logo 应用领域
尔必达 - ELPIDA 内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
65页 670K
描述
1G bits DDR2 SDRAM organized as 33,554,432 words x 8 banks.

EDE1108AASE-5C-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA68,9X19,32
针数:68Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.83Is Samacsys:N
访问模式:MULTI BANK PAGE BURST最长访问时间:0.5 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):267 MHz
I/O 类型:COMMON交错的突发长度:4,8
JESD-30 代码:R-PBGA-B68JESD-609代码:e1
长度:20.7 mm内存密度:1073741824 bit
内存集成电路类型:DDR DRAM内存宽度:8
功能数量:1端口数量:1
端子数量:68字数:134217728 words
字数代码:128000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:128MX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA68,9X19,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):260
电源:1.8 V认证状态:Not Qualified
刷新周期:8192座面最大高度:1.12 mm
自我刷新:YES连续突发长度:4,8
子类别:DRAMs最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.2 mmBase Number Matches:1

EDE1108AASE-5C-E 数据手册

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DATA SHEET  
1G bits DDR2 SDRAM  
EDE1104AASE (256M words × 4 bits)  
EDE1108AASE (128M words × 8 bits)  
Features  
Description  
The EDE1104AASE is a 1G bits DDR2 SDRAM  
Power supply: VDD, VDDQ = 1.8V ± 0.1V  
organized as 33,554,432 words × 4 bits × 8 banks.  
Double-data-rate architecture: two data transfers per  
clock cycle  
The EDE1108AASE is a 1G bits DDR2 SDRAM  
organized as 16,777,216 words × 8 bits × 8 banks.  
They are packaged in 68-ball FBGA (µBGA) package.  
Bi-directional, differential data strobe (DQS and  
/DQS) is transmitted/received with data, to be used in  
capturing data at the receiver  
DQS is edge aligned with data for READs: center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge: data  
and data mask referenced to both edges of DQS  
8 internal banks for concurrent operation  
Data mask (DM) for write data  
Burst lengths: 4, 8  
/CAS Latency (CL): 3, 4, 5  
Auto precharge operation for each burst access  
Auto refresh and self refresh modes  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
SSTL_18 compatible I/O  
Posted CAS by programmable additive latency for  
better command and data bus efficiency  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
Programmable RDQS, /RDQS output for making × 8  
organization compatible to × 4 organization  
/DQS, (/RDQS) can be disabled for single-ended  
Data Strobe operation.  
FBGA (µBGA) package with lead free solder  
(Sn-Ag-Cu)  
Document No. E0404E20 (Ver. 2.0)  
Date Published April 2005 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2003-2005  

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