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EDE1104ACBG-5C-E PDF预览

EDE1104ACBG-5C-E

更新时间: 2024-09-18 06:55:55
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
82页 778K
描述
1G bits DDR2 SDRAM

EDE1104ACBG-5C-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA60,9X11,32
针数:60Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.32
风险等级:5.84Is Samacsys:N
访问模式:MULTI BANK PAGE BURST最长访问时间:0.5 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):266 MHz
I/O 类型:COMMON交错的突发长度:4,8
JESD-30 代码:R-PBGA-B60长度:11.5 mm
内存密度:1073741824 bit内存集成电路类型:DDR DRAM
内存宽度:4功能数量:1
端口数量:1端子数量:60
字数:268435456 words字数代码:256000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:256MX4
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA60,9X11,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8 V
认证状态:Not Qualified刷新周期:8192
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:4,8子类别:DRAMs
最大压摆率:0.26 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:11 mm
Base Number Matches:1

EDE1104ACBG-5C-E 数据手册

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DATA SHEET  
1G bits DDR2 SDRAM  
EDE1104ACBG (256M words × 4 bits)  
EDE1108ACBG (128M words × 8 bits)  
EDE1116ACBG (64M words × 16 bits)  
Features  
Specifications  
Density: 1G bits  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
32M words × 4 bits × 8 banks (EDE1104ACBG)  
16M words × 8 bits × 8 banks (EDE1108ACBG)  
8M words × 16 bits × 8 banks (EDE1116ACBG)  
Package  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
60-ball FBGA (EDE1104/1108ACBG)  
84-ball FBGA (EDE1116ACBG)  
Lead-free (RoHS compliant)  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Power supply: VDD, VDDQ = 1.8V ± 0.1V  
Data rate  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
800Mbps/667Mbps/533Mbps (max.)  
1KB page size (EDE1104/1108ACBG)  
Row address: A0 to A13  
Data mask (DM) for write data  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Column address: A0 to A9, A11 (EDE1104ACBG)  
A0 to A9 (EDE1108ACBG)  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
2KB page size (EDE1116ACBG)  
Row address: A0 to A12  
Column address: A0 to A9  
Eight internal banks for concurrent operation  
Interface: SSTL_18  
Programmable RDQS, /RDQS output for making × 8  
organization compatible to × 4 organization  
/DQS, (/RDQS) can be disabled for single-ended  
Data Strobe operation  
Burst lengths (BL): 4, 8  
Burst type (BT):  
Sequential (4, 8)  
Interleave (4, 8)  
/CAS Latency (CL): 3, 4, 5, 6  
Precharge: auto precharge option for each burst  
access  
Driver strength: normal/weak  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Operating case temperature range  
TC = 0°C to +95°C  
Document No. E1173E40 (Ver. 4.0)  
Date Published September 2008 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2007-2008  

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