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EDD51163DBH-5BLS-F PDF预览

EDD51163DBH-5BLS-F

更新时间: 2024-11-07 06:55:55
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率
页数 文件大小 规格书
60页 759K
描述
512M bits DDR Mobile RAM™ WTR (Wide Temperature Range), Low Power Function

EDD51163DBH-5BLS-F 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:VFBGA,针数:60
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.28风险等级:5.28
访问模式:FOUR BANK PAGE BURST最长访问时间:5 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PBGA-B60
JESD-609代码:e1长度:8.5 mm
内存密度:536870912 bit内存集成电路类型:DDR DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:60
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-25 °C组织:32MX16
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
认证状态:Not Qualified座面最大高度:1 mm
自我刷新:YES最大供电电压 (Vsup):1.95 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM宽度:7.5 mm
Base Number Matches:1

EDD51163DBH-5BLS-F 数据手册

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PRELIMINARY DATA SHEET  
512M bits DDR Mobile RAM  
WTR (Wide Temperature Range), Low Power Function  
EDD51163DBH-LS (32M words × 16 bits)  
Specifications  
Features  
Density: 512M bits  
Organization: 8M words × 16 bits × 4 banks  
DLL is not implemented  
Low power consumption  
Package: 60-ball FBGA  
Partial Array Self-Refresh (PASR)  
Lead-free (RoHS compliant) and Halogen-free  
Power supply: VDD, VDDQ = 1.7V to 1.95V  
Data rate: 400Mbps/333Mbps (max.)  
2KB page size  
Row address: A0 to A12  
Column address: A0 to A9  
Four internal banks for concurrent operation  
Interface: LVCMOS  
Burst lengths (BL): 2, 4, 8, 16  
Burst type (BT):  
Auto Temperature Compensated Self-Refresh  
(ATCSR) by built-in temperature sensor  
Deep power-down mode  
Double-data-rate architecture; two data transfers per  
one clock cycle  
The high-speed data transfer is realized by the 2 bits  
prefetch pipelined architecture  
Bi-directional data strobe (DQS) is transmitted  
/received with data for capturing data at the receiver.  
Data inputs, outputs, and DM are synchronized with  
DQS  
DQS is edge-aligned with data for READs; center-  
Sequential (2, 4, 8, 16)  
Interleave (2, 4, 8, 16)  
/CAS Latency (CL): 3  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
Commands entered on each positive CK edge: data  
Precharge: auto precharge option for each burst  
and data mask referenced to both edges of DQS  
access  
Data mask (DM) for write data  
Driver strength: normal, 1/2, 1/4, 1/8  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period: 7.8µs  
Operating ambient temperature range  
TA = 25°C to +85°C  
Burst termination by burst stop command and  
precharge command  
Wide temperature range  
TA = 25°C to +85°C  
Document No. E1433E30 (Ver. 3.0)  
Date Published October 2009 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2008-2009  

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