DATA SHEET
512M bits DDR SDRAM
EDD5104ADTA (128M words × 4 bits)
EDD5108ADTA (64M words × 8 bits)
EDD5116ADTA (32M words × 16 bits)
Pin Configurations
Description
The EDD5104AD, the EDD5108AD and the
EDD5116AD are 512M bits Double Data Rate (DDR)
SDRAM. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in standard 66-pin
plastic TSOP (II).
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
NC
VDD
DQ0
VDD
DQ0
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
2
VSS VSS VSS
DQ15 DQ7 NC
VSSQ VSSQ VSSQ
VDDQ
NC
DQ0
VSSQ
NC
VDDQ VDDQ
3
4
5
6
7
8
NC
DQ1
DQ1
DQ2
DQ14 NC
NC
DQ13 DQ6 DQ3
VDDQ VDDQ VDDQ
VSSQ VSSQ
NC
DQ2
DQ3
DQ4
DQ12 NC
NC
NC
DQ11 DQ5 NC
VSSQ VSSQ VSSQ
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
VDDQ VDDQ
9
NC
DQ3
DQ5
DQ6
10
11
12
13
14
15
DQ10 NC
NC
DQ9 DQ4 DQ2
VDDQ VDDQ VDDQ
VSSQ VSSQ
NC
NC
DQ7
NC
DQ8 NC
NC
NC
NC
NC
Features
VDDQ VDDQ
NC LDQS 16
VSSQ VSSQ VSSQ
UDQS DQS DQS
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Data Rate: 333Mbps/266Mbps (max.)
NC
VDD
NC
NC
VDD
NC
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
NC
NC
NC
VREF VREF VREF
VSS VSS VSS
• Double Data Rate architecture; two data transfers per
NC
NC
UDM DM
/CK /CK /CK
CK
CK CK
CKE CKE CKE
NC
NC NC
DM
clock cycle
/WE
/CAS
/RAS
/CS
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
NC
NC
BA0
BA1
A12 A12 A12
A11 A11 A11
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
• Data inputs, outputs, and DM are synchronized with
A9
A8
A7
A6
A5
A4
A9
A8
A7
A6
A5
A4
A9
A8
A7
A6
A5
A4
DQS
A10(AP) A10(AP)
A0
A1
A2
A3
VDD
A0
A1
A2
A3
VDD
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
VSS VSS VSS
• Differential clock inputs (CK and /CK)
X 16
• DLL aligns DQ and DQS transitions with CK
X 8
X 4
transitions
• Commands entered on each positive CK edge; data
(Top view)
and data mask referenced to both edges of DQS
A0 to A12
BA0, BA1
DQ0 to DQ15
Address input
Bank select address
Data-input/output
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Programmable output driver strength: normal/weak
• Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
DQS, LDQS, UDQS Input and output data strobe
/CS
Chip select
/RAS
/CAS
/WE
DM, LDM, UDM
CK
/CK
CKE
VREF
VDD
VSS
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Auto refresh
Self refresh
VDDQ
VSSQ
NC
Document No. E0384E30 (Ver. 3.0)
Date Published January 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2004
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