PRELIMINARY DATA SHEET
512M bits DDR SDRAM
EDD5104ABTA (128M words × 4 bits)
EDD5108ABTA (64M words × 8 bits)
Pin Configurations
Description
The EDD5104AB is a 512M bits Double Data Rate
(DDR) SDRAM organized as 33,554,432 words × 4 bits
× 4 banks. The EDD5108AB is a 512M bits DDR
SDRAM organized as 16,777,216 words × 8 bits × 4
banks. Read and write operations are performed at the
cross points of the CK and the /CK. This high-speed
data transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode resistor, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
/xxx indicates active low signal.
66-pin TSOP(II)10.16mm(400)
VDD
NC
VDD
DQ0
VSS VSS
DQ7 NC
VSSQ VSSQ
1
2
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDDQ VDDQ
3
NC
NC
NC
NC
4
DQ0
DQ1
DQ6 DQ3
VDDQ VDDQ
5
VSSQ VSSQ
6
NC
NC
NC
DQ2
NC
NC
7
8
DQ5 NC
VSSQ VSSQ
VDDQ VDDQ
9
NC
DQ1
VSSQ VSSQ
NC
NC
VDDQ VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
NC
DQ3
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DQ4 DQ2
VDDQ VDDQ
They are packaged in standard 66-pin plastic TSOP
NC
NC
NC
NC
NC
NC
(II)10.16mm(400).
VSSQ VSSQ
DQS DQS
Features
NC
NC
VDD
NC
NC
NC
• 2.5 V power supply: VDDQ = 2.5V ± 0.2V
: VDD = 2.5V ± 0.2V
• Data Rate: 333Mbps/266Mbps (max.)
VREF VREF
VSS VSS
NC
DM
/CK
CK
DM
/CK
CK
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
• Double Data Rate architecture; two data transfers per
CKE CKE
clock cycle
NC
A12
A11
A9
NC
A12
A11
A9
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
A10(AP) A10(AP)
A8
A8
• Data inputs, outputs, and DM are synchronized with
A0
A1
A2
A3
VDD
A0
A1
A2
A3
VDD
A7
A7
DQS
A6
A6
A5
A5
• 4 internal banks for concurrent operation
A4
A4
• DQS is edge aligned with data for READs; center
VSS VSS
aligned with data for WRITEs
X 8
• Differential clock inputs (CK and /CK)
X 4
• DLL aligns DQ and DQS transitions with CK
(Top view)
transitions
A0 to A12
BA0, BA1
DQ0 to DQ7
DQS
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Auto precharge option for each burst access
• 2.5 V (SSTL_2 compatible) I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: 8192 refresh cycles/64ms
7.8µs maximum average periodic refresh interval
• 2 variations of refresh
/CS
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
Auto refresh
Self refresh
VDDQ
VSSQ
NC
Document No. E0237E30 (Ver. 3.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
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