PRELIMINARY DATA SHEET
256M bits DDR SDRAM
EDD2508AMTA (32M words × 8 bits)
EDD2516AMTA (16M words × 16 bits)
Pin Configurations
Description
The EDD2508AM is a 256M bits Double Data Rate
(DDR) SDRAM organized as 8,388,608 words × 8 bits
× 4 banks. The EDD2516AM is a 256M bits DDR
SDRAM organized as 4,194,304 words × 16 bits × 4
banks. Read and write operations are performed at the
cross points of the CK and the /CK. This high-speed
data transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode resister, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
They are packaged in standard 66-pin plastic TSOP
(II).
/xxx indicates active low signal.
66-pin plastic TSOP(II)
VDD
DQ0
VDD
DQ0
66
1
2
VSS VSS
DQ15 DQ7
VSSQ VSSQ
DQ14 NC
DQ13 DQ6
VDDQ VDDQ
DQ12 NC
DQ11 DQ5
VSSQ VSSQ
DQ10 NC
DQ9 DQ4
VDDQ VDDQ
DQ8 NC
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VDDQ VDDQ
3
NC
DQ1
DQ1
DQ2
4
5
VSSQ VSSQ
6
NC
DQ2
DQ3
DQ4
7
8
VDDQ VDDQ
9
NC
DQ3
VSSQ VSSQ
NC
NC
VDDQ VDDQ
NC LDQS
NC
VDD
NC
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ7
NC
NC
NC
VSSQ VSSQ
UDQS DQS
Features
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
NC
VREF VREF
VSS VSS
UDM DM
/CK /CK
• 2.5 V power supply: VDDQ = 2.5V ± 0.2V
: VDD = 2.5V ± 0.2V
• Data rate: 333Mbps/266Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
CK
CKE CKE
NC
NC
CK
NC
BA0
BA1
A12 A12
A11 A11
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
A9
A8
A7
A6
A5
A4
A9
A8
A7
A6
A5
A4
A10(AP) A10(AP) 28
A0
A1
A2
A3
VDD
A0 29
A1 30
A2 31
A3 32
VDD 33
• Data inputs, outputs, and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
VSS VSS
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
X 16
X 8
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ15
Address input
Bank select address
Data-input/output
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
DQS, UDQS, LDQS Input and output data strobe
/CS
Chip select
• Data mask (DM) for write data
• Auto precharge option for each burst access
• 2.5 V (SSTL_2 compatible) I/O
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: 8192 refresh cycles/64ms
⎯ 7.8μs maximum average periodic refresh interval
• 2 variations of refresh
/RAS
/CAS
/WE
DM, UDM, LDM
CK
/CK
CKE
VREF
VDD
VSS
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
VDDQ
VSSQ
NC
⎯ Auto refresh
⎯ Self refresh
Document No. E0405E10 (Ver. 1.0)
This product became EOL in March, 2007.
Date Published September 2003 (K) Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2003
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