PRELIMINARY DATA SHEET
256M bits DDR SDRAM
WTR (Wide Temperature Range)
EDD2516AKTA-TI (16M words × 16 bits)
EDD2516AKTA-LI (16M words × 16 bits)
Pin Configurations
Description
The EDD2516AK is a 256M bits Double Data Rate
(DDR) SDRAM organized as 4,194,304 words × 16 bits
× 4 banks. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in standard 66-pin
plastic TSOP (II).
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
VSS
1
2
3
4
5
6
7
8
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Features
• Power supply : VDD, VDDQ = 2.5V ± 0.2V
• Data rate: 333Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional data strobe (DQS) transmitted /received
with data, for capturing data at the receiver
CKE
NC
A12
A11
A9
• Data inputs, outputs, and DM are synchronized with
DQS
NC
BA0
BA1
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
A10(AP) 28
A0 29
A1 30
A2 31
A3 32
VDD 33
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
(Top view)
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
A0 to A12
BA0, BA1
Address input
Bank select address
DQ0 to DQ15 Data-input/output
UDQS/LDQS Input and output data strobe
/CS
Chip select
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Programmable output driver strength: normal/weak
• Refresh cycles: 8192 refresh cycles/64ms
⎯ 7.8μs maximum average periodic refresh interval
• 2 variations of refresh
⎯ Auto refresh
⎯ Self refresh
• Ambient temperature range: −40 to +85°C
/RAS
/CAS
/WE
UDM/LDM
CK
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
/CK
CKE
Differential clock input
Clock enable
VREF
VDD
VSS
VDDQ
VSSQ
NC
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0435E20 (Ver. 2.0)
Date Published February 2004 (K) Japan
URL: http://www.elpida.com
This product became EOL in April, 2007.
©Elpida Memory, Inc. 2003-2004