PRELIMINARY DATA SHEET
256M bits DDR SDRAM
WTR (Wide Temperature Range)
EDD2508AKTA-LI (32M words × 8 bits)
Description
Pin Configurations
The EDD2508AK is a 256M bits DDR SDRAM
organized as 8,388,608 words × 8 bits × 4 banks.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2 bits prefetch-pipelined
architecture. Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
It is packaged in standard 66-pin plastic TSOP (II).
/xxx indicates active low signal.
66-pin Plastic TSOP(II)
VDD
DQ0
VDDQ
NC
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
1
2
3
4
DQ1
VSSQ
NC
5
6
7
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NC
NC
/WE
/CAS
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Features
• Power supply : VDDQ = 2.5V ± 0.2V
: VDD = 2.5V ± 0.2V
• Data rate: 333Mbps (max.)
• Double Data Rate architecture; two data transfers per
clock cycle
NC
VSSQ
DQS
NC
VREF
VSS
DM
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
/CK
CK
/RAS 23
44 CKE
/CS
NC
BA0
BA1
43
42
41
40
NC
A12
A11
A9
24
25
26
27
• Data inputs, outputs, and DM are synchronized with
DQS
• 4 internal banks for concurrent operation
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
A10(AP) 28
A0 29
A1 30
A2 31
A3 32
VDD 33
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
(Top view)
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
A0 to A12
BA0, BA1
DQ0 to DQ7
DQS
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
• Data mask (DM) for write data
• Auto precharge option for each burst access
• SSTL_2 compatible I/O
/CS
• Programmable burst length (BL): 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Programmable output driver strength: normal/weak
• Refresh cycles: 8192 refresh cycles/64ms
⎯ 7.8μs maximum average periodic refresh interval
• 2 variations of refresh
⎯ Auto refresh
⎯ Self refresh
• Ambient temperature range: –40 to +85°C
/RAS
/CAS
/WE
DM
CK
/CK
CKE
VREF
VDD
VSS
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
VDDQ
VSSQ
NC
Document No. E0434E10 (Ver. 1.0)
Date Published November 2003 (K) Japan
URL: http://www.elpida.com
This product became EOL in April, 2007.
©Elpida Memory, Inc. 2003