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EDD2508AKTA-5B-E

更新时间： 2024-11-06 22:30:39
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
48页 534K
描述
256M bits DDR SDRAM (32M words x 8 bits, DDR400)

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EDD2508AKTA-5B-E 数据手册

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PRELIMINARY DATA SHEET  
256M bits DDR SDRAM  
EDD2508AKTA-5-E (32M words × 8 bits, DDR400)  
Description  
Pin Configurations  
The EDD2508AKTA-5 is a 256M bits DDR SDRAM  
organized as 8,388,608 words × 8 bits × 4 banks.  
Read and write operations are performed at the cross  
points of the CK and the /CK. This high-speed data  
transfer is realized by the 2 bits prefetch-pipelined  
architecture. Data strobe (DQS) both for read and  
write are available for high speed and reliable data bus  
design. By setting extended mode register, the on-chip  
Delay Locked Loop (DLL) can be set enable or disable.  
/xxx indicates active low signal.  
66-pin Plastic TSOP(II)  
VDD  
DQ0  
VDDQ  
NC  
VSS  
DQ7  
VSSQ  
NC  
DQ6  
VDDQ  
NC  
DQ5  
VSSQ  
NC  
DQ4  
VDDQ  
NC  
1
2
3
4
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
DQ1  
VSSQ  
NC  
5
6
7
DQ2  
VDDQ  
NC  
DQ3  
VSSQ  
NC  
NC  
VDDQ  
NC  
8
9
It is packaged in 66-pin plastic TSOP (II).  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
Features  
NC  
• Power supply: VDD, VDDQ = 2.6V ± 0.1V  
• Data rate: 400Mbps (max.)  
VSSQ  
DQS  
NC  
VREF  
VSS  
DM  
NC  
VDD  
NC  
• Double Data Rate architecture; two data transfers per  
clock cycle  
NC  
• Bi-directional data strobe (DQS) is transmitted  
/WE  
/CAS  
/RAS  
/CS  
/CK  
CK  
/received with data for capturing data at the receiver  
CKE  
NC  
A12  
A11  
A9  
A8  
A7  
A6  
A5  
• Data inputs, outputs, and DM are synchronized with  
DQS  
NC  
• 4 internal banks for concurrent operation  
BA0  
BA1  
A10(AP)  
A0  
A1  
A2  
A3  
VDD  
• DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
• Differential clock inputs (CK and /CK)  
• DLL aligns DQ and DQS transitions with CK  
A4  
VSS  
transitions  
• Commands entered on each positive CK edge; data  
(Top view)  
and data mask referenced to both edges of DQS  
• Data mask (DM) for write data  
• Auto precharge option for each burst access  
• SSTL_2 compatible I/O  
• Programmable burst length (BL): 2, 4, 8  
• Programmable /CAS latency (CL): 3  
• Programmable output driver strength: normal/weak  
• Refresh cycles: 8192 refresh cycles/64ms  
7.8µs maximum average periodic refresh interval  
• 2 variations of refresh  
A0 to A12  
BA0, BA1  
DQ0 to DQ7  
DQS  
Address input  
Bank select address  
Data-input/output  
Input and output data strobe  
Chip select  
Row address strobe command  
Column address strobe command  
Write enable  
Input mask  
Clock input  
Differential clock input  
Clock enable  
Input reference voltage  
Power for internal circuit  
Ground for internal circuit  
Power for DQ circuit  
Ground for DQ circuit  
No connection  
/CS  
/RAS  
/CAS  
/WE  
DM  
CK  
/CK  
CKE  
VREF  
VDD  
VSS  
Auto refresh  
Self refresh  
• TSOP (II) package with lead free solder (Sn-Bi)  
VDDQ  
VSSQ  
NC  
Document No. E0609E20 (Ver. 2.0)  
Date Published February 2005 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2004-2005  
1234567...48

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