Datasheet > EDD2508AETA

EDD2508AETA

更新时间： 2024-09-17 03:33:27

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
52页	574K
描述
256M bits DDR SDRAM

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中文翻译

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数据手册

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EDD2508AETA 数据手册

DATA SHEET

256M bits DDR SDRAM

EDD2508AETA (32M words × 8 bits)

EDD2516AETA (16M words × 16 bits)

Features

Specifications

• Density: 256M bits

• Organization

8M words × 8 bits × 4 banks (EDD2508AETA)

4M words × 16 bits × 4 banks (EDD2516AETA)

• Package: 66-pin plastic TSOP (II)

Lead-free (RoHS compliant)

• Power supply:

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 2 bits

prefetch pipelined architecture

• Bi-directional data strobe (DQS) is transmitted

/received with data for capturing data at the receiver

• Data inputs, outputs, and DM are synchronized with

DQS

DDR400:

VDD, VDDQ = 2.6V ± 0.1V

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

DDR333, 266: VDD, VDDQ = 2.5V ± 0.2V

• Data rate: 400Mbps/333Mbps/266Mbps (max.)

• Four internal banks for concurrent operation

• Interface: SSTL_2

• Burst lengths (BL): 2, 4, 8

• Burst type (BT):

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

Sequential (2, 4, 8)

Interleave (2, 4, 8)

• /CAS Latency (CL): 2, 2.5, 3

• Precharge: auto precharge option for each burst

access

• Driver strength: normal/weak

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

Average refresh period: 7.8µs

• Operating ambient temperature range

TA = 0°C to +70°C

Document No. E0859E50 (Ver. 5.0)

Date Published September 2007 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2006-2007

12 3 4 5 6 7...52

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