Datasheet > EDD2504AKTA-E

EDD2504AKTA-E

更新时间： 2024-11-06 22:30:39

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
49页	537K
描述
256M bits DDR SDRAM (64M words x 4 bits)

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EDD2504AKTA-E 数据手册

DATA SHEET

256M bits DDR SDRAM

EDD2504AKTA-E (64M words × 4 bits)

Description

Pin Configurations

The EDD2504AKTA is a 256M bits Double Data Rate

(DDR) SDRAM organized as 16,777,216 words × 4 bits

× 4 banks. Read and write operations are performed at

the cross points of the CK and the /CK. This high-

speed data transfer is realized by the 2 bits prefetch-

pipelined architecture. Data strobe (DQS) both for

read and write are available for high speed and reliable

data bus design. By setting extended mode register,

the on-chip Delay Locked Loop (DLL) can be set

enable or disable. It is packaged in 66-pin plastic

TSOP (II).

/xxx indicates active low signal.

66-pin Plastic TSOP(II)

VDD

VSS

VSSQ

DQ3

VDDQ

DQ0

VSSQ

VDDQ

DQ1

VSSQ

VDDQ

58 VSSQ

DQ2

VDDQ

Features

• Power supply : VDDQ = 2.5V ± 0.2V

: VDD = 2.5V ± 0.2V

• Data rate: 333Mbps/266Mbps (max.)

VSSQ

DQS

VREF

VSS

/CK

CKE

A12

A11

VDD

• Double Data Rate architecture; two data transfers per

clock cycle

/WE

/CAS

/RAS

/CS

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

• Data inputs, outputs, and DM are synchronized with

BA0

BA1

A10(AP)

DQS

• 4 internal banks for concurrent operation

• DQS is edge aligned with data for READs; center

VDD

VSS

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

(Top view)

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Auto precharge option for each burst access

• SSTL_2 compatible I/O

• Programmable burst length (BL): 2, 4, 8

• Programmable /CAS latency (CL): 2, 2.5

• Programmable output driver strength: normal/weak

• Refresh cycles: 8192 refresh cycles/64ms

7.8µs maximum average periodic refresh interval

• 2 variations of refresh

A0 to A12

BA0, BA1

DQ0 to DQ3

DQS

Address input

Bank select address

Data-input/output

Input and output data strobe

Chip select

Row address strobe command

Column address strobe command

Write enable

Input mask

Clock input

Differential clock input

Clock enable

Input reference voltage

Power for internal circuit

Ground for internal circuit

Power for DQ circuit

Ground for DQ circuit

No connection

/CS

/RAS

/CAS

/WE

/CK

CKE

VREF

VDD

VSS

Auto refresh

Self refresh

• TSOP (II) package with lead free solder (Sn-Bi)

VDDQ

VSSQ

Document No. E0610E10 (Ver. 1.0)

Date Published November 2004 (K) Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2004

12 3 4 5 6 7...49

中文翻译

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与EDD2504AKTA-E相关器件

型号	品牌	获取价格	描述	数据表
EDD2508AETA	ELPIDA	获取价格	256M bits DDR SDRAM
EDD2508AETA-5B-E	ELPIDA	获取价格	256M bits DDR SDRAM
EDD2508AETA-5C-E	ELPIDA	获取价格	256M bits DDR SDRAM
EDD2508AETA-6B-E	ELPIDA	获取价格	256M bits DDR SDRAM
EDD2508AETA-7A-E	ELPIDA	获取价格	256M bits DDR SDRAM
EDD2508AETA-7B-E	ELPIDA	获取价格	256M bits DDR SDRAM
EDD2508AJTA	ELPIDA	获取价格	256M bits DDR SDRAM
EDD2508AJTA-6B	ELPIDA	获取价格	256M bits DDR SDRAM
EDD2508AJTA-7A	ELPIDA	获取价格	256M bits DDR SDRAM
EDD2508AJTA-7B	ELPIDA	获取价格	256M bits DDR SDRAM

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