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EDD1232ABBH PDF预览

EDD1232ABBH

更新时间: 2024-09-17 03:33:27
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
51页 531K
描述
128M bits DDR SDRAM

EDD1232ABBH 数据手册

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DATA SHEET  
128M bits DDR SDRAM  
EDD1232ABBH (4M words × 32 bits)  
Specifications  
Features  
Density: 128M bits  
• ×32 organization  
Organization  
Double-data-rate architecture; two data transfers per  
clock cycle  
1M words × 32 bits × 4 banks  
Package: 144-ball FBGA  
Lead-free (RoHS compliant)  
Power supply: VDD, VDDQ = 2.5V 0.125V  
Data rate: 400Mbps (max.)  
Four internal banks for concurrent operation  
Interface: SSTL_2  
The high-speed data transfer is realized by the 2 bits  
prefetch pipelined architecture  
Bi-directional data strobe (DQS) is transmitted  
/received with data for capturing data at the receiver  
Data inputs, outputs, and DM are synchronized with  
DQS  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Burst lengths (BL): 2, 4, 8  
Burst type (BT):  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
Sequential (2, 4, 8)  
Interleave (2, 4, 8)  
/CAS Latency (CL): 3  
Precharge: auto precharge operation for each burst  
access  
transitions  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Data mask (DM) for write data  
Driver strength: weak/matched  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 4096 cycles/32ms  
Average refresh period: 7.8μs  
Operating ambient temperature range  
TA = 0°C to +70°C  
Document No. E0874E40 (Ver. 4.0)  
Date Published April 2007 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
©Elpida Memory, Inc. 2006-2007  

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