Datasheet > EDD1232AABH

EDD1232AABH

更新时间： 2024-09-16 22:30:39

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
50页	603K
描述
128M bits DDR SDRAM (4M words x 32 bits)

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EDD1232AABH 数据手册

DATA SHEET

128M bits DDR SDRAM

EDD1232AABH (4M words × 32 bits)

Description

Features

The EDD1232AABH is a 128M bits DDR SDRAM

organized as 1,048,576 words × 32 bits × 4 banks.

Read and write operations are performed at the cross

points of the CK and the /CK. This high-speed data

transfer is realized by the 2 bits prefetch-pipelined

architecture. Data strobe (DQS) both for read and

write are available for high speed and reliable data bus

design. By setting extended mode register, the on-chip

Delay Locked Loop (DLL) can be set enable or disable.

• Power supply: VDDQ = 2.5V ± 0.2V

: VDD = 2.5V ± 0.2V

• Data rate: 333Mbps/266Mbps (max.)

• Double Data Rate architecture; two data transfers per

clock cycle

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

• Data inputs, outputs, and DM are synchronized with

It is packaged in 144-ball FBGA package.

DQS

• 4 internal banks for concurrent operation

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Auto precharge option for each burst access

• SSTL_2 compatible I/O

• Programmable burst length (BL): 2, 4, 8

• Programmable /CAS latency (CL): 2, 2.5, 3

• Programmable output driver strength: half/weak

• Refresh cycles: 4096 refresh cycles/32ms

7.8µs maximum average periodic refresh interval

• 2 variations of refresh

Auto refresh

Self refresh

• FBGA package with lead free solder (Sn-Ag-Cu)

RoHS compliant

Document No. E0533E50 (Ver. 5.0)

Date Published June 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2004-2005

12 3 4 5 6 7...50

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与EDD1232AABH相关器件

型号	品牌	获取价格	描述	数据表
EDD1232AABH-5C-E	ELPIDA	获取价格	DDR DRAM, 4MX32, 0.7ns, CMOS, PBGA144, LEAD FREE, FBGA-144
EDD1232AABH-6B-E	ELPIDA	获取价格	128M bits DDR SDRAM (4M words x 32 bits)
EDD1232AABH-7A-E	ELPIDA	获取价格	128M bits DDR SDRAM (4M words x 32 bits)
EDD1232AABH-7B-E	ELPIDA	获取价格	DDR DRAM, 4MX32, 0.75ns, CMOS, PBGA144, LEAD FREE, FBGA-144
EDD1232AAFA	ELPIDA	获取价格	128M bits DDR SDRAM (4M words x 32 bits)
EDD1232AAFA-5C-E	ELPIDA	获取价格	DDR DRAM, 4MX32, 0.7ns, CMOS, PQFP100, LEAD FREE, PLASTIC, LQFP-100
EDD1232AAFA-6B-E	ELPIDA	获取价格	128M bits DDR SDRAM (4M words x 32 bits)
EDD1232AAFA-7A-E	ELPIDA	获取价格	128M bits DDR SDRAM (4M words x 32 bits)
EDD1232AAFA-7B-E	ELPIDA	获取价格	DDR DRAM, 4MX32, 0.75ns, CMOS, PQFP100, LEAD FREE, PLASTIC, LQFP-100
EDD1232ABBH	ELPIDA	获取价格	128M bits DDR SDRAM