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EDBA164B2PR PDF预览

EDBA164B2PR

更新时间: 2024-11-12 02:46:55
品牌 Logo 应用领域
镁光 - MICRON 动态存储器双倍数据速率光电二极管
页数 文件大小 规格书
152页 2119K
描述
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Features

EDBA164B2PR 数据手册

 浏览型号EDBA164B2PR的Datasheet PDF文件第2页浏览型号EDBA164B2PR的Datasheet PDF文件第3页浏览型号EDBA164B2PR的Datasheet PDF文件第4页浏览型号EDBA164B2PR的Datasheet PDF文件第5页浏览型号EDBA164B2PR的Datasheet PDF文件第6页浏览型号EDBA164B2PR的Datasheet PDF文件第7页 
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM  
Features  
LPDDR2 SDRAM  
EDB8164B4PR, EDB8164B4PK, EDB8164B4PT, EDBA164B2PR  
Options  
Marking  
Features  
• Ultra-low-voltage core and I/O power supplies  
• Frequency range  
– 533 MHz (data rate: 1066 Mb/s/pin)  
• 4n prefetch DDR architecture  
• 8 internal banks for concurrent operation  
• Multiplexed, double data rate, command/address  
inputs; commands entered on each CK_t/CK_c  
edge  
• Bidirectional/differential data strobe per byte of  
data (DQS_t/DQS_c)  
• Programmable READ and WRITE latencies (RL/WL)  
• Burst length: 4, 8, and 16  
• Per-bank refresh for concurrent operation  
• Auto temperature-compensated self refresh  
(ATCSR) by built-in temperature sensor  
• Partial-array self refresh (PASR)  
• Deep power-down mode (DPD)  
• Selectable output drive strength (DS)  
• Clock-stop capability  
• Density/Page Size  
– 8Gb/2-CS – dual die  
– 16Gb/4-CS – quad die  
• Organization  
81  
A1  
– x64  
64  
B
• VDD1/VDD2/VDDQ: 1.8V/1.2V/1.2V  
• Revision  
– Dual die  
4
2
– Quad die  
• FBGA “green” package  
– 12mm x 12mm x 0.8mm, 216-ball  
PoP FBGA package, dual die  
– 12mm x 12mm x 0.8mm, 216-ball  
PoP FBGA package, dual die  
– 12mm x 12mm x 1.0mm, 216-ball  
PoP FBGA package, quad die  
– 14mm x 14mm x 0.7mm, 220-ball  
PoP FBGA package, dual die  
• Timing – cycle time  
– 1.875ns @ RL = 8  
PR  
PT  
PR  
PK  
-1D  
• Lead-free (RoHS-compliant) and halogen-free  
packaging  
• Special options  
– Non-Automotive  
blank  
• Operating temperature range  
– From –30°C to +85°C  
– From –40°C to +85°C  
– From –40°C to +105°C  
blank  
IT  
AT  
Table 1: Key Timing Parameters  
Speed  
Grade  
Clock Rate Data Rate  
(MHz)  
(Mb/s/pin)  
RL  
WL  
1D  
533  
1066  
8
4
Table 2: S4 Configuration Addressing  
Architecture  
128 Meg x 64  
256 Meg x 64  
Die configuration  
Row addressing  
Column addressing  
Number of die  
Die per rank  
16 Meg x 32 x 8 banks x 2 channel  
32 Meg x 32 x 8 banks x 2 channel  
16K A[13:0]  
16K A[13:0]  
1K A[9:0]  
1K A[9:0]  
2
1
1
4
2
2
Ranks per channel  
1. A channel is a complete LPDRAM interface, including command/address and data pins.  
Note:  
09005aef85eb530a  
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
© 2014 Micron Technology, Inc. All rights reserved.  
1
Products and specifications discussed herein are subject to change by Micron without notice.  
 
 

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