Datasheet > EBJ51RD8BAFA-DJ-E

EBJ51RD8BAFA-DJ-E

更新时间： 2024-11-22 07:56:59

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
21页	236K
描述
DDR DRAM Module, 64MX72, 0.255ns, CMOS, ROHS COMPLIANT, DIMM-240

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PRELIMINARY DATA SHEET

512MB Registered DDR3 SDRAM DIMM

EBJ51RD8BAFA (64M words × 72 bits, 1 Rank)

Specifications

Features

• Density: 512MB

• Organization

⎯ 64M words × 72 bits, 1 rank

• Mounting 9 pieces of 512M bits DDR3 SDRAM

sealed in FBGA

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• Package: 240-pin socket type dual in line memory

module (DIMM)

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

⎯ PCB height: 30.0mm

⎯ Lead pitch: 1.0mm

⎯ Lead-free (RoHS compliant)

• Power supply: VDD = 1.5V 0.075V

• Data rate: 1333Mbps/1066Mbps/800Mbps (max.)

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Eight internal banks for concurrent operation

(components)

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• Interface: SSTL_15

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9

• /CAS write latency (CWL): 5, 6

• On-Die-Termination (ODT) for better signal quality

⎯ Synchronous ODT

⎯ Dynamic ODT

⎯ Asynchronous ODT

• Precharge: auto precharge option for each burst

access

• Refresh: auto-refresh, self-refresh

• Refresh cycles

• Multi Purpose Register (MPR) for temperature read

out

• ZQ calibration for DQ drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset

function

⎯ Average refresh period

7.8μs at 0°C ≤ TC ≤ +85°C

3.9μs at +85°C < TC ≤ +95°C

• Operating case temperature range

⎯ TC = 0°C to +95°C

• SRT range:

⎯ Normal/extended

⎯ Auto/manual self-refresh

• Programmable Output driver impedance control

• 1 piece of registering clock driver and 1 piece of

serial EEPROM (256 bytes EEPROM) for Presence

Detect (PD)

Document No. E1188E10 (Ver. 1.0)

Date Published November 2007 (K) Japan

Printed in Japan

URL: http://www.elpida.com

12 3 4 5 6 7...21

中文翻译

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与EBJ51RD8BAFA-DJ-E相关器件

型号	品牌	获取价格	描述	数据表
EBJ51UD8BAFA-8A-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ51UD8BAFA-8C-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.4ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ51UD8BAFA-AC-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.3ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ51UD8CAFA-DG-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.255ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ51UD8CAFA-DJ-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.255ns, CMOS, ROHS COMPLIANT, DIMM-240
EBJ51UE6BASA-8A-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.4ns, CMOS, ROHS COMPLIANT, SO-DIMM, 204 PIN
EBJ51UE6BASA-8C-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.4ns, CMOS, ROHS COMPLIANT, SO-DIMM, 204 PIN
EBJ51UE6BASA-AC-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.3ns, CMOS, ROHS COMPLIANT, SO-DIMM, 204 PIN
EBJ51UE6BASA-AE-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.3ns, CMOS, ROHS COMPLIANT, SO-DIMM, 204 PIN
EBJ51UE6BASA-AG-E	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.3ns, CMOS, ROHS COMPLIANT, SO-DIMM, 204 PIN

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