Datasheet > EBJ21UE8BAU0-AC-F

EBJ21UE8BAU0-AC-F

更新时间： 2024-11-22 07:55:19

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
18页	200K
描述
DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, SODIMM-204

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PRELIMINARY DATA SHEET

2GB DDR3 SDRAM SO-DIMM

EBJ21UE8BAU0 (256M words × 64 bits, 2 Ranks)

Specifications

Features

• Density: 2GB

• Double-data-rate architecture; two data transfers per

clock cycle

• Organization

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

256M words × 64 bits, 2 ranks

• Mounting 16 pieces of 1G bits DDR3 SDRAM sealed

in FBGA

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• Package: 204-pin socket type small outline dual in

line memory module (SO-DIMM)

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

PCB height: 30.0mm

Lead pitch: 0.6mm

• Differential clock inputs (CK and /CK)

Lead-free (RoHS compliant)

(EBJ21UE8BAU0-xx-E)

• DLL aligns DQ and DQS transitions with CK

transitions

Lead-free (RoHS compliant) and Halogen-free

(EBJ21UE8BAU0-xx-F)

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Power supply: VDD = 1.5V ± 0.075V

• Data mask (DM) for write data

• Data rate: 1333Mbps/1066Mbps/800Mbps (max.)

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• Eight internal banks for concurrent operation

(components)

• On-Die-Termination (ODT) for better signal quality

Synchronous ODT

• Interface: SSTL_15

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• /CAS Latency (CL): 6, 7, 8, 9

Dynamic ODT

Asynchronous ODT

• /CAS write latency (CWL): 5, 6, 7

• Multi Purpose Register (MPR) for temperature read

out

• Precharge: auto precharge option for each burst

access

• ZQ calibration for DQ drive and ODT

• Refresh: auto-refresh, self-refresh

• Refresh cycles

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset

function

Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• SRT range:

Normal/extended

• Operating case temperature range

TC = 0°C to +95°C

Auto/manual self-refresh

• Programmable Output driver impedance control

Document No. E1244E30 (Ver. 3.0)

Date Published October 2008 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2007-2008

12 3 4 5 6 7...18

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与EBJ21UE8BAU0-AC-F相关器件

型号	品牌	获取价格	描述	数据表
EBJ21UE8BAU0-AE-E	ELPIDA	获取价格	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, SODIMM-204
EBJ21UE8BAU0-AE-F	ELPIDA	获取价格	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, SODIMM-204
EBJ21UE8BAU0-AG-F	ELPIDA	获取价格	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, SODIMM-204
EBJ21UE8BAU0-DG-E	ELPIDA	获取价格	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, SODIMM-204
EBJ21UE8BAU0-DG-F	ELPIDA	获取价格	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, SODIMM-204
EBJ21UE8BAU0-DJ-E	ELPIDA	获取价格	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, SODIMM-204
EBJ21UE8BAU0-DJ-F	ELPIDA	获取价格	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, SODIMM-204
EBJ21UE8BAW0-8A-E	ELPIDA	获取价格	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, DIMM-240
EBJ21UE8BAW0-8C-E	ELPIDA	获取价格	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, DIMM-240
EBJ21UE8BAW0-AC-E	ELPIDA	获取价格	DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, DIMM-240

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