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EBJ21UE8BASA-8C-E PDF预览

EBJ21UE8BASA-8C-E

更新时间: 2024-11-09 20:10:31
品牌 Logo 应用领域
尔必达 - ELPIDA 时钟动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
18页 200K
描述
DDR DRAM Module, 256MX64, CMOS, ROHS COMPLIANT, SO-DIMM, 204 PIN

EBJ21UE8BASA-8C-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DMA包装说明:DIMM, DIMM204,24
针数:204Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.83访问模式:DUAL BANK PAGE BURST
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):400 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N204
内存密度:17179869184 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:64功能数量:1
端口数量:1端子数量:204
字数:268435456 words字数代码:256000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:256MX64
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM204,24
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.5 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES最大待机电流:0.192 A
子类别:DRAMs最大压摆率:2.6 mA
最大供电电压 (Vsup):1.575 V最小供电电压 (Vsup):1.425 V
标称供电电压 (Vsup):1.5 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:NO LEAD端子节距:0.6 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

EBJ21UE8BASA-8C-E 数据手册

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DATA SHEET  
2GB DDR3 SDRAM SO-DIMM  
EBJ21UE8BASA (256M words × 64 bits, 2 Ranks)  
Specifications  
Features  
Density: 2GB  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 8 bits  
prefetch pipelined architecture  
256M words × 64 bits, 2 ranks  
Mounting 16 pieces of 1G bits DDR3 SDRAM sealed  
in FBGA  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
Package: 204-pin socket type small outline dual in  
line memory module (SO-DIMM)  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
PCB height: 30.0mm  
Lead pitch: 0.6mm  
Differential clock inputs (CK and /CK)  
Lead-free (RoHS compliant)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Power supply: VDD = 1.5V ± 0.075V  
Data rate: 1333Mbps/1066Mbps/800Mbps (max.)  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Eight internal banks for concurrent operation  
(components)  
Data mask (DM) for write data  
Interface: SSTL_15  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Burst lengths (BL): 8 and 4 with Burst Chop (BC)  
/CAS Latency (CL): 6, 7, 8, 9  
On-Die-Termination (ODT) for better signal quality  
Synchronous ODT  
/CAS write latency (CWL): 5, 6, 7  
Dynamic ODT  
Precharge: auto precharge option for each burst  
access  
Asynchronous ODT  
Refresh: auto-refresh, self-refresh  
Refresh cycles  
Multi Purpose Register (MPR) for temperature read  
out  
ZQ calibration for DQ drive and ODT  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Programmable Partial Array Self-Refresh (PASR)  
/RESET pin for Power-up sequence and reset  
Operating case temperature range  
TC = 0°C to +95°C  
function  
SRT range:  
Normal/extended  
Auto/manual self-refresh  
Programmable Output driver impedance control  
Temperature sensor functionality with EEPROM.  
Document No. E1225E30 (Ver. 3.0)  
Date Published December 2008 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2007-2008  

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