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EBJ20UF8BDU0-GN-F PDF预览

EBJ20UF8BDU0-GN-F

更新时间: 2024-01-10 23:11:16
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
16页 140K
描述
DRAM

EBJ20UF8BDU0-GN-F 技术参数

生命周期:Obsolete包装说明:DIMM,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
访问模式:SINGLE BANK PAGE BURST其他特性:AUTO/SELF REFRESH; SEATED HGT-NOM; WD-MAX
JESD-30 代码:R-XZMA-N204JESD-609代码:e4
长度:67.6 mm内存密度:17179869184 bit
内存集成电路类型:DDR DRAM MODULE内存宽度:64
功能数量:1端口数量:1
端子数量:204字数:268435456 words
字数代码:256000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:256MX64封装主体材料:UNSPECIFIED
封装代码:DIMM封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY座面最大高度:30 mm
自我刷新:YES最大供电电压 (Vsup):1.575 V
最小供电电压 (Vsup):1.425 V标称供电电压 (Vsup):1.5 V
表面贴装:NO技术:CMOS
温度等级:OTHER端子面层:GOLD
端子形式:NO LEAD端子节距:0.6 mm
端子位置:ZIG-ZAG宽度:3.8 mm
Base Number Matches:1

EBJ20UF8BDU0-GN-F 数据手册

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DATA SHEET  
2GB DDR3 SDRAM SO-DIMM  
EBJ20UF8BDU0 (256M words × 64 bits, 1 Rank)  
Specifications  
Features  
Density: 2GB  
Double-data-rate architecture: two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 8 bits  
prefetch pipelined architecture  
256M words × 64 bits, 1 rank  
Mounting 8 pieces of 2G bits DDR3 SDRAM sealed  
in FBGA  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
Package: 204-pin socket type small outline dual  
in-line memory module (SO-DIMM)  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
PCB height: 30.0mm  
Lead pitch: 0.6mm  
Differential clock inputs (CK and /CK)  
Lead-free (RoHS compliant) and Halogen-free  
Power supply: VDD = 1.5V ± 0.075V  
Data rate: 1600Mbps/1333Mbps (max.)  
Backward compatible to1066Mbps/800Mbps/667Mbps  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Eight internal banks for concurrent operation  
Data mask (DM) for write data  
(components)  
Posted /CAS by programmable additive latency for  
Interface: SSTL_15  
better command and data bus efficiency  
Burst lengths (BL): 8 and 4 with Burst Chop (BC)  
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11  
/CAS write latency (CWL): 5, 6, 7, 8  
On-Die-Termination (ODT) for better signal quality  
Synchronous ODT  
Dynamic ODT  
Precharge: auto precharge option for each burst  
Asynchronous ODT  
access  
Multi Purpose Register (MPR) for pre-defined pattern  
Refresh: auto-refresh, self-refresh  
Refresh cycles  
read out  
ZQ calibration for DQ drive and ODT  
Average refresh period  
Programmable Partial Array Self-Refresh (PASR)  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
/RESET pin for Power-up sequence and reset  
function  
Operating case temperature range  
TC = 0°C to +95°C  
SRT range:  
Normal/extended  
Programmable Output driver impedance control  
Document No. E1795E20 (Ver. 2.0)  
Date Published September 2011 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2011  

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