Datasheet > EBE51UD8ABFV

EBE51UD8ABFV

更新时间： 2024-09-18 06:55:27

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
22页	225K
描述
512MB Unbuffered DDR2 SDRAM HYPER DIMM™

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EBE51UD8ABFV 数据手册

PRELIMINARY DATA SHEET

512MB Unbuffered DDR2 SDRAM

HYPER DIMM

EBE51UD8ABFV (64M words × 64 bits, 1 Rank)

Description

Features

The EBE51UD8ABFV is 64M words × 64 bits, 1 rank

DDR2 SDRAM unbuffered module, mounting 8 pieces

of 512M bits DDR2 SDRAM sealed in FBGA package.

Read and write operations are performed at the cross

points of the CK and the /CK. This high-speed data

transfer is realized by the 4 bits prefetch-pipelined

architecture. Data strobe (DQS and /DQS) both for

read and write are available for high speed and reliable

data bus design. By setting extended mode register,

the on-chip Delay Locked Loop (DLL) can be set

enable or disable. This module provides high density

mounting without utilizing surface mount technology.

Decoupling capacitors are mounted beside each FBGA

on the module board.

• 240-pin socket type dual in line memory module

(DIMM)

PCB height: 30.0mm

Lead pitch: 1.0mm

Lead-free

• 1.85V power supply

• Data rate: 667Mbps/600Mbps (max.)

• SSTL_18 compatible I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,

which may result in electrical defects.

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

• Four internal banks for concurrent operation

(components)

• Data mask (DM) for write data

• Burst lengths: 4, 8

• /CAS Latency (CL): 3, 4, 5

• Auto precharge operation for each burst access

• Auto refresh and self refresh modes

• 7.8µs average periodic refresh interval

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

Document No. E0528E12 (Ver. 1.2)

This product became EOL in April, 2005.

Date Published February 2006 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2004-2006

12 3 4 5 6 7...22

中文翻译

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与EBE51UD8ABFV相关器件

型号	品牌	获取价格	描述	数据表
EBE51UD8ABFV-AE-E	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM HYPER DIMM™
EBE51UD8ABFV-BE-E	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM HYPER DIMM™
EBE51UD8AEFA	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
EBE51UD8AEFA-4A-E	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
EBE51UD8AEFA-5C-E	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
EBE51UD8AEFA-6	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words ?64 bits, 1 Rank)
EBE51UD8AEFA-6E-E	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words ?64 bits, 1 Rank)
EBE51UD8AGFA	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
EBE51UD8AGFA-4A-E	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
EBE51UD8AGFA-5C-E	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)

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