Datasheet > EBE51RD8AGFA

EBE51RD8AGFA

更新时间： 2024-09-17 22:05:27

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
23页	193K
描述
512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)

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EBE51RD8AGFA 数据手册

DATA SHEET

512MB Registered DDR2 SDRAM DIMM

EBE51RD8AGFA (64M words × 72 bits, 1 Rank)

Description

Features

The EBE51RD8AGFA is a 64M words × 72 bits, 1 rank

DDR2 SDRAM Module, mounting 9 pieces of DDR2

SDRAM sealed in FBGA (µBGA^) package. Read and

write operations are performed at the cross points of

the CK and the /CK. This high-speed data transfer is

realized by the 4bits prefetch-pipelined architecture.

Data strobe (DQS and /DQS) both for read and write

are available for high speed and reliable data bus

design. By setting extended mode register, the on-chip

Delay Locked Loop (DLL) can be set enable or disable.

This module provides high density mounting without

• 240-pin socket type dual in line memory module

(DIMM)

PCB height: 30.0mm

Lead pitch: 1.0mm

Lead-free (RoHS compliant)

• Power supply: VDD = 1.8V ± 0.1V

• Data rate: 667Mbps/533Mbps/400Mbps (max.)

• SSTL_18 compatible I/O

• Double-data-rate architecture: two data transfers per

clock cycle

utilizing surface mount technology.

capacitors are mounted beside each FBGA (µBGA) on

the module board.

Decoupling

• Bi-directional, data strobe (DQS and /DQS) is

transmitted /received with data, to be used in

capturing data at the receiver

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,

which may result in electrical defects.

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Four internal banks for concurrent operation

(components)

• Data mask (DM) for write data

• Burst length: 4, 8

• /CAS latency (CL): 3, 4, 5

• Auto precharge option for each burst access

• Auto refresh and self refresh modes

• Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

• 1 piece of PLL clock driver, 1 pieces of register driver

and 1 piece of serial EEPROM (2k bits EEPROM) for

Presence Detect (PD)

Document No. E0793E20 (Ver. 2.0)

Date Published October 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2005

12 3 4 5 6 7...23

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与EBE51RD8AGFA相关器件

型号	品牌	获取价格	描述	数据表
EBE51RD8AGFA-4A-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AGFA-5C-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AGFA-6E-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AJFA	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM
EBE51RD8AJFA-4A-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM
EBE51RD8AJFA-5C-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM
EBE51RD8AJFA-6E-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM
EBE51UD8ABFA	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
EBE51UD8ABFA-4A	ELPIDA	获取价格	DDR DRAM Module, 64MX64, 0.6ns, CMOS, DIMM-240
EBE51UD8ABFA-4A-E	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)

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