Datasheet > 存储 > DRAM> EBE51RD8AEFA-6

EBE51RD8AEFA-6

更新时间： 2024-11-07 06:55:27

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
22页	192K
描述
512MB Registered DDR2 SDRAM DIMM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EBE51RD8AEFA-6 数据手册

DATA SHEET

512MB Registered DDR2 SDRAM DIMM

EBE51RD8AEFA-6 (64M words × 72 bits, 1 Rank)

Description

Features

The EBE51RD8AEFA is a 64M words × 72 bits, 1 rank

DDR2 SDRAM Module, mounting 9 pieces of DDR2

SDRAM sealed in FBGA package. Read and write

operations are performed at the cross points of the CK

and the /CK. This high-speed data transfer is realized

by the 4bits prefetch-pipelined architecture. Data

strobe (DQS and /DQS) both for read and write are

available for high speed and reliable data bus design.

By setting extended mode register, the on-chip Delay

Locked Loop (DLL) can be set enable or disable. This

module provides high density mounting without utilizing

surface mount technology. Decoupling capacitors are

mounted beside each FBGA on the module board.

• 240-pin socket type dual in line memory module

(DIMM)

PCB height: 30.0mm

Lead pitch: 1.0mm

Lead-free (RoHS compliant)

• Power supply: VDD = 1.8V ± 0.1V

• Data rate: 667Mbps (max.)

• SSTL_18 compatible I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, data strobe (DQS and /DQS) is

transmitted /received with data, to be used in

capturing data at the receiver

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,

which may result in electrical defects.

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Four internal banks for concurrent operation

(components)

• Data mask (DM) for write data

• Burst length: 4, 8

• /CAS latency (CL): 3, 4, 5

• Auto precharge option for each burst access

• Auto refresh and self refresh modes

• Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

• 1 piece of PLL clock driver, 1 pieces of register driver

and 1 piece of serial EEPROM (2k bits EEPROM) for

Presence Detect (PD)

Document No. E0789E11 (Ver. 1.1)

Date Published February 2006 (K) Japan

Printed in Japan

This Product became EOL in November, 2006.

URL: http://www.elpida.com

Elpida Memory, Inc. 2005-2006

12 3 4 5 6 7...22

中文翻译

下载PDF

与EBE51RD8AEFA-6相关器件

型号	品牌	获取价格	描述	数据表
EBE51RD8AEFA-6E-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM
EBE51RD8AGFA	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AGFA-4A-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AGFA-5C-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AGFA-6E-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
EBE51RD8AJFA	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM
EBE51RD8AJFA-4A-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM
EBE51RD8AJFA-5C-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM
EBE51RD8AJFA-6E-E	ELPIDA	获取价格	512MB Registered DDR2 SDRAM DIMM
EBE51UD8ABFA	ELPIDA	获取价格	512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)

与EBE51RD8AEFA-6相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

18
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

15
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

38
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

36

产品中心

服务支持

精选活动

关于我们

帮助中心

EBE51RD8AEFA-6

EBE51RD8AEFA-6 数据手册

与EBE51RD8AEFA-6相关器件

与EBE51RD8AEFA-6相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

EBE51RD8AEFA-6

EBE51RD8AEFA-6 数据手册

与EBE51RD8AEFA-6相关器件

与EBE51RD8AEFA-6相关文章

您还可以找

您在本页遇到什么问题？