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EBE51RD8AEFA-4A-E PDF预览

EBE51RD8AEFA-4A-E

更新时间: 2024-09-17 22:05:23
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
22页 186K
描述
512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)

EBE51RD8AEFA-4A-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM240,40
针数:240Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.84Is Samacsys:N
访问模式:SINGLE BANK PAGE BURST最长访问时间:0.6 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N240
内存密度:4831838208 bit内存集成电路类型:DDR DRAM MODULE
内存宽度:72功能数量:1
端口数量:1端子数量:240
字数:67108864 words字数代码:64000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:64MX72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM240,40
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
峰值回流温度(摄氏度):260电源:1.8 V
认证状态:Not Qualified刷新周期:8192
自我刷新:YES最大待机电流:0.5 A
子类别:Other Memory ICs最大压摆率:3.33 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:NO LEAD端子节距:1 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

EBE51RD8AEFA-4A-E 数据手册

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DATA SHEET  
512MB Registered DDR2 SDRAM DIMM  
EBE51RD8AEFA (64M words × 72 bits, 1 Rank)  
Description  
Features  
The EBE51RD8AEFA is a 64M words × 72 bits, 1 rank  
DDR2 SDRAM Module, mounting 9 pieces of DDR2  
SDRAM sealed in FBGA (µBGA) package. Read and  
write operations are performed at the cross points of  
the CK and the /CK. This high-speed data transfer is  
realized by the 4bits prefetch-pipelined architecture.  
Data strobe (DQS and /DQS) both for read and write  
are available for high speed and reliable data bus  
design. By setting extended mode register, the on-chip  
Delay Locked Loop (DLL) can be set enable or disable.  
This module provides high density mounting without  
240-pin socket type dual in line memory module  
(DIMM)  
PCB height: 30.0mm  
Lead pitch: 1.0mm  
Lead-free  
Power supply: VDD, VDDQ = 1.8V ± 0.1V  
Data rate: 533Mbps/400Mbps (max.)  
SSTL_18 compatible I/O  
Double-data-rate architecture: two data transfers per  
clock cycle  
utilizing surface mount technology.  
capacitors are mounted beside each FBGA (µBGA) on  
the module board.  
Decoupling  
Bi-directional, data strobe (DQS and /DQS) is  
transmitted /received with data, to be used in  
capturing data at the receiver  
DQS is edge aligned with data for READs; center  
aligned with data for WRITEs  
Note: Do not push the components or drop the  
modules in order to avoid mechanical defects,  
which may result in electrical defects.  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Four internal banks for concurrent operation  
(components)  
Data mask (DM) for write data  
Burst length: 4, 8  
/CAS latency (CL): 3, 4, 5  
Auto precharge option for each burst access  
Auto refresh and self refresh modes  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Posted CAS by programmable additive latency for  
better command and data bus efficiency  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
/DQS can be disabled for single-ended Data Strobe  
operation  
1 piece of PLL clock driver, 1 pieces of register driver  
and 1 piece of serial EEPROM (2k bits EEPROM) for  
Presence Detect (PD)  
Document No. E0645E30 (Ver. 3.0)  
Date Published April 2005 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2005  

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