Datasheet > EBE41RE4AAHA

EBE41RE4AAHA

更新时间： 2024-11-08 22:05:11

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
22页	196K
描述
4GB Registered DDR2 SDRAM DIMM (512M words x 72 bits, 2 Ranks)

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EBE41RE4AAHA 数据手册

DATA SHEET

4GB Registered DDR2 SDRAM DIMM

EBE41RE4AAHA (512M words × 72 bits, 2 Ranks)

Description

Features

The EBE41RE4AAHA is a 512M words × 72 bits, 2

ranks DDR2 SDRAM Module, mounting 36 pieces of

1G bits DDR2 SDRAM with sFBGA stacking

technology. Read and write operations are performed

at the cross points of the CK and the /CK. This high-

speed data transfer is realized by the 4bits prefetch-

pipelined architecture. Data strobe (DQS and /DQS)

both for read and write are available for high speed and

reliable data bus design. By setting extended mode

set enable or disable. This module provides high

density mounting without utilizing surface mount

• 240-pin socket type dual in line memory module

(DIMM)

PCB height: 30.0mm

Lead pitch: 1.0mm

Lead-free (RoHS compliant)

• Power supply: VDD, VDDQ = 1.8V ± 0.1V

• Data rate: 533Mbps/400Mbps (max.)

• SSTL_18 compatible I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, data strobe (DQS and /DQS) is

transmitted /received with data, to be used in

capturing data at the receiver

technology.

Decoupling capacitors are mounted

beside each SDRAM on the module board.

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

Note: Do not push the cover or drop the modules in

order to avoid mechanical defects, which may

result in electrical defects.

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Eight internal banks for concurrent operation

(Components)

• Burst length: 4, 8

• /CAS latency (CL): 3, 4, 5

• Auto precharge option for each burst access

• Auto refresh and self refresh modes

• Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

• 1 piece of PLL clock driver, 2 pieces of register

drivers and 1 piece of serial EEPROM (2k bits

EEPROM) for Presence Detect (PD)

Document No. E0629E20 (Ver. 2.0)

Date Published September 2005 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2005

12 3 4 5 6 7...22

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与EBE41RE4AAHA相关器件

型号	品牌	获取价格	描述	数据表
EBE41RE4AAHA-4A-E	ELPIDA	获取价格	4GB Registered DDR2 SDRAM DIMM (512M words x 72 bits, 2 Ranks)
EBE41RE4AAHA-5C-E	ELPIDA	获取价格	4GB Registered DDR2 SDRAM DIMM (512M words x 72 bits, 2 Ranks)
EBE41RE4ABHA	ELPIDA	获取价格	4GB Registered DDR2 SDRAM DIMM
EBE41RE4ABHA-4A-E	ELPIDA	获取价格	4GB Registered DDR2 SDRAM DIMM
EBE41RE4ABHA-5C-E	ELPIDA	获取价格	4GB Registered DDR2 SDRAM DIMM
EBE41RE4ABHA-6E-E	ELPIDA	获取价格	4GB Registered DDR2 SDRAM DIMM
EBE41RE4ACFA	ELPIDA	获取价格	4GB Registered DDR2 SDRAM DIMM
EBE41RE4ACFA-4A-E	ELPIDA	获取价格	4GB Registered DDR2 SDRAM DIMM
EBE41RE4ACFA-5C-E	ELPIDA	获取价格	4GB Registered DDR2 SDRAM DIMM
EBE41RE4ACFA-6E-E	ELPIDA	获取价格	4GB Registered DDR2 SDRAM DIMM

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