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EBE41FE4AAHA-5C-E PDF预览

EBE41FE4AAHA-5C-E

更新时间： 2024-11-09 21:02:15
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器
页数 文件大小 规格书
2页 150K
描述
DRAM,

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EBE41FE4AAHA-5C-E 技术参数

生命周期：Transferred包装说明：,
Reach Compliance Code：unknown风险等级：5.75
Base Number Matches：1

EBE41FE4AAHA-5C-E 数据手册

 浏览型号EBE41FE4AAHA-5C-E的Datasheet PDF文件第2页 
Fully Buffered DIMM  
Main Memory for Next Generation Servers  
The Fully Buffered Dual in-line Memory Module (FB-DIMM) provides advanced performance for  
next-generation servers and offers unprecedented speed up to 4.8Gbps data rate.  
Elpida Memory began sample shipment in December 2004 and continues to expand its FB-DIMM lineup in  
step with the growth of the market.  
Features of the Fully Buffered DIMM  
In the new FB-DIMM, all signals — clock, address,  
command and data — to and from the DRAM on the  
module are buffered at the high-speed Advanced Memory  
Buffer (AMB) chip located on the DIMM. This helps to  
secure the DRAM timing margins during high-speed  
operation, with a much shorter signal path between the  
DRAM and the AMB.  
ꢀ FB-DIMM  
Point-to-Point architecture (Serial connection)  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
Memory  
Controller  
AMB  
AMB  
AMB  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
Up to  
8 DIMMs  
can be  
loaded  
The FB-DIMM also adopts a Point-to-Point connection on  
the bus between the memory controller and the DIMM, as  
well as between the DIMMs themselves. This allows  
increased bus speed with a shorter connection path. It  
also greatly improves the maximum number of DIMMs that  
can be loaded on the bus — up to eight 2-rank DIMMs —  
with less concern about signal degradation.  
ꢀ Standard DIMM  
Stub-bus architecture (Parallel connection)  
Memory  
Controller  
By comparison, existing standard Registered DIMMs have a  
stub-bus architecture along the memory bus between each  
DIMM and the memory controller. As the memory  
frequency increases, the controller must reduce the  
number of DIMMs loaded on the memory bus to secure the  
signal quality and the timing margin along the lengthy  
signal path between the DRAM devices on the module and  
the controller on the motherboard. This limitation has  
presented a bottleneck in achieving improved performance  
in server applications where both high-speed and  
high-density are essential.  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
DRAM  
Document No. E0632E30 (Ver.3.0)  
Date Published August 2005 (K) Japan  
Printed in Japan  
© Elpida Memory, Inc. 2004-2005  
http://www.elpida.com  
12

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