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EBE41AF4A1QA PDF预览

EBE41AF4A1QA

更新时间: 2024-09-17 06:55:27
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
27页 226K
描述
4GB VLP Registered DDR2 SDRAM DIMM

EBE41AF4A1QA 数据手册

 浏览型号EBE41AF4A1QA的Datasheet PDF文件第2页浏览型号EBE41AF4A1QA的Datasheet PDF文件第3页浏览型号EBE41AF4A1QA的Datasheet PDF文件第4页浏览型号EBE41AF4A1QA的Datasheet PDF文件第5页浏览型号EBE41AF4A1QA的Datasheet PDF文件第6页浏览型号EBE41AF4A1QA的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
4GB VLP Registered DDR2 SDRAM DIMM  
EBE41AF4A1QA (512M words × 72 bits, 2 Ranks)  
Specifications  
Features  
Density: 4GB  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
512M words × 72 bits, 2 ranks  
Mounting 18 pieces of 2G bits DDR2 SDRAM with  
DDP (FBGA)  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
DDP: 2 pieces of 1Gb chips sealed in one package  
Package: 240-pin very low profile registered  
dual in line memory module (VLP RDIMM)  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
PCB height: 18.3mm  
Differential clock inputs (CK and /CK)  
Lead pitch: 1.0mm  
DLL aligns DQ and DQS transitions with CK  
transitions  
Lead-free (RoHS compliant)  
Power supply: VDD = 1.8V ± 0.1V  
Data rate: 667Mbps (max.)  
Commands entered on each positive CK edge; data  
referenced to both edges of DQS  
Posted /CAS by programmable additive latency for  
Eight internal banks for concurrent operation  
better command and data bus efficiency  
(components)  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Interface: SSTL_18  
Termination for better signal quality  
Burst lengths (BL): 4, 8  
/CAS Latency (CL): 3, 4, 5  
/DQS can be disabled for single-ended Data Strobe  
operation  
Precharge: auto precharge option for each burst  
access  
1 piece of PLL clock driver, 2 pieces of register driver  
and 1 piece of serial EEPROM (2K bits EEPROM) for  
Presence Detect (PD)  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Operating case temperature range  
TC = 0°C to +95°C  
Document No. E1165E10 (Ver. 1.0)  
Date Published September 2007 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2007  

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