Datasheet > EBE25RC8AAFA

EBE25RC8AAFA

更新时间： 2022-12-21 09:22:59

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
22页	194K
描述
256MB Registered DDR2 SDRAM DIMM

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EBE25RC8AAFA 数据手册

PRELIMINARY DATA SHEET

256MB Registered DDR2 SDRAM DIMM

EBE25RC8AAFA (32M words × 72 bits, 1 Rank)

Description

Features

The EBE25RC8AAFA is a 32M words × 72 bits, 1 rank

DDR2 SDRAM Module, mounting 9 pieces of DDR2

SDRAM sealed in FBGA package. Read and write

operations are performed at the cross points of the CK

and the /CK. This high-speed data transfer is realized

by the 4bits prefetch-pipelined architecture. Data

strobe (DQS and /DQS) both for read and write are

available for high speed and reliable data bus design.

By setting extended mode register, the on-chip Delay

Locked Loop (DLL) can be set enable or disable. This

module provides high density mounting without utilizing

surface mount technology. Decoupling capacitors are

mounted beside each FBGA on the module board.

• 240-pin socket type dual in line memory module

(DIMM)

PCB height: 30.0mm

Lead pitch: 1.0mm

Lead-free

• 1.8V power supply

• Data rate: 533Mbps/400Mbps (max.)

• 1.8 V (SSTL_18 compatible) I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, data strobe (DQS and /DQS) is

transmitted /received with data, to be used in

capturing data at the receiver

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,

which may result in electrical defects.

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Four internal banks for concurrent operation

(Component)

• Data mask (DM) for write data

• Burst length: 4, 8

• /CAS latency (CL): 3, 4, 5

• Auto precharge option for each burst access

• Auto refresh and self refresh modes

• 7.8µs average periodic refresh interval

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

• 1 piece of PLL clock driver, 1 pieces of register driver

and 1 piece of serial EEPROM (2k bits EEPROM) for

Presence Detect (PD)

Document No. E0470E11 (Ver. 1.1)

Date Published February 2006 (K) Japan

URL: http://www.elpida.com

This product became EOL in April, 2005.

Elpida Memory, Inc. 2004-2006

12 3 4 5 6 7...22

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