Datasheet > EBE25EC8AAFA

EBE25EC8AAFA

更新时间： 2022-12-21 23:43:19

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
22页	191K
描述
256MB Unbuffered DDR2 SDRAM DIMM

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

EBE25EC8AAFA 数据手册

PRELIMINARY DATA SHEET

256MB Unbuffered DDR2 SDRAM DIMM

EBE25EC8AAFA (32M words × 72 bits, 1 Rank)

Description

Features

The EBE25EC8AAFA is 32M words × 72 bits, 1 rank

DDR2 SDRAM unbuffered module, mounting 9 pieces

of 256M bits DDR2 SDRAM sealed in FBGA (µBGA^)

package. Read and write operations are performed at

the cross points of the CK and the /CK. This high-

speed data transfer is realized by the 4 bits prefetch-

pipelined architecture. Data strobe (DQS and /DQS)

both for read and write are available for high speed and

reliable data bus design. By setting extended mode

set enable or disable. This module provides high

density mounting without utilizing surface mount

• 240-pin socket type dual in line memory module

(DIMM)

PCB height: 30.0mm

Lead pitch: 1.0mm

Lead-free

• 1.8V power supply

• Data rate: 533Mbps/400Mbps (max.)

• 1.8V (SSTL_18 compatible) I/O

• Double-data-rate architecture: two data transfers per

clock cycle

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

technology.

Decoupling capacitors are mounted

beside each FBGA (µBGA) on the module board.

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

Note: Do not push the components or drop the

modules in order to avoid mechanical defects,

which may result in electrical defects.

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

• Four internal banks for concurrent operation

(components)

• Data mask (DM) for write data

• Burst lengths: 4, 8

• /CAS Latency (CL): 3, 4, 5

• Auto precharge operation for each burst access

• Auto refresh and self refresh modes

• 7.8µs average periodic refresh interval

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• /DQS can be disabled for single-ended Data Strobe

operation

Document No. E0466E10 (Ver. 1.0)

Date Published February 2004 (K) Japan

URL: http://www.elpida.com

This product became EOL in April, 2005.

Elpida Memory, Inc. 2004

12 3 4 5 6 7...22

下载PDF

与EBE25EC8AAFA相关器件

型号	品牌	描述	获取价格	数据表
EBE25EC8AAFA-4A-E	ELPIDA	256MB Unbuffered DDR2 SDRAM DIMM	获取价格
EBE25EC8AAFA-4C-E	ELPIDA	256MB Unbuffered DDR2 SDRAM DIMM	获取价格
EBE25EC8AAFA-5C-E	ELPIDA	256MB Unbuffered DDR2 SDRAM DIMM	获取价格
EBE25RC8AAFA	ELPIDA	256MB Registered DDR2 SDRAM DIMM	获取价格
EBE25RC8AAFA-4A-E	ELPIDA	256MB Registered DDR2 SDRAM DIMM	获取价格
EBE25RC8AAFA-4C-E	ELPIDA	256MB Registered DDR2 SDRAM DIMM	获取价格