EBE10UE8AFSA-6E-F

更新时间： 2024-02-13 04:32:10

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
29页	251K
描述
1GB DDR2 SDRAM SO-DIMM

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DATA SHEET

1GB DDR2 SDRAM SO-DIMM

EBE10UE8AFSA (128M words × 64 bits, 1 Rank)

Specifications

Features

• Density: 1GB

• Double-data-rate architecture; two data transfers per

clock cycle

• Organization

• The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

128M words × 64 bits, 1 rank

• Mounting 8 pieces of 1G bits DDR2 SDRAM sealed

in FBGA

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

• Package: 200-pin socket type small outline dual in

line memory module (SO-DIMM)

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

PCB height: 30.0mm

Lead pitch: 0.6mm

• Differential clock inputs (CK and /CK)

Lead-free (RoHS compliant) and Halogen-free

• Power supply: VDD = 1.8V ± 0.1V

• Data rate: 800Mbps/667Mbps (max.)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Eight internal banks for concurrent operation

(components)

• Data mask (DM) for write data

• Interface: SSTL_18

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• Burst lengths (BL): 4, 8

• /CAS Latency (CL): 3, 4, 5, 6

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• Precharge: auto precharge option for each burst

• /DQS can be disabled for single-ended Data Strobe

access

operation

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Operating case temperature range

TC = 0°C to +95°C

Document No. E1450E20 (Ver.2.0)

Date Published July 2009 (K) Japan

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2009

12 3 4 5 6 7...29

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