Datasheet > E1-32XS

E1-32XS

更新时间： 2024-09-17 23:49:43

品牌	Logo	应用领域
其他 - ETC		/
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2页	153K
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E1-32XS

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E1-32XS 数据手册

E1-32XS

RISC/DSP Processor

A 32-Bit microcontroller design with an integrated RISC/DSP

core architecture offering maximum power efﬁciency in portable

multimedia and consumer electronics applications

RISC and DSP Working Together

The new E1-32XS offers a powerful RISC architecture with integrated

DSP support and 16KByte on-chip SRAM. This unique integrated

design delivers a power-efﬁcient and cost effective solution for a wide

range of portable multimedia and consumer electronic products.

Now developers can have the best of both worlds – a fast RISC

processor for control functions, and a DSP unit for efﬁcient algorithm

execution – yet avoid the silicon overhead and software complexity

of a dual-core design.

Integrated Core Functionality

The Hyperstone core has been speciﬁcally designed to combine both

RISC and DSP functions – but as an single integrated core and

instruction set, rather than a combination of a 2 different cores on

single piece of silicon. This fully integrated core is based on a single

processor model with a single instruction stream. Simple and efﬁcient

communication between the RISC and DSP units is achieved via the

96-way 32-bit internal register set. A major factor in achieving the

high power-efﬁciency delivered by this design is the parallel opera-

tion of three functional blocks of the integrated core: the RISC ALU,

the DSP Unit and the Load/Store Unit. The integrated architecture

allows instructions to be streamed through all 3 units simultaneously

to deliver a peak performance of 720 MOPS.

Integrated RISC/DSP core with peak performance of 720 MOPS at 180MHz

Single RISC/DSP instruction stream for rapid development and

simpliﬁed debugging environment

Parallel execution of Load/Store, RISC and DSP Units

Very high code density using variable length 16, 32 and 48 bit instructions

Extremely short interrupt latency - starts code execution in less than 50 ns @180MHz

Low power consumption of 200mW@180MHz at 2.5 V

using 0.25m technology

Power efﬁcient performance of integrated core delivers peak

throughput of 3.6GOPS/Watt

Available in 16 or 32-bit external bus interface

versions, both with full internal 32-bit execution

Available as “off-the-shelf” standard LQFP

devices or as IP core for ASIC integration

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