E-STE100A

更新时间： 2024-11-02 03:34:47

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		控制器 PC 以太网局域网（LAN）标准
页数	文件大小	规格书
82页	797K
描述
PCI 10/100 Ethernet controller with integrated PHY (3.3V)

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数据手册

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E-STE100A 数据手册

STE10/100A

PCI 10/100 Ethernet controller with integrated PHY (3.3V)

Features

■ IEEE802.3u 100BASE-TX and IEEE802.3

10BASE-T compliant

■ Support for IEEE802.3x flow control

■ IEEE802.3u auto-negotiation support for

PQFP128 (14mm x 20mm x 2.7mm)

10BASE-T and 100BASE-TX

■ PCI bus interface rev. 2.2 compliant

Description

■ ACPI and PCI power management standard

compliant

The STE10/100A is a high performing PCI fast

ethernet controller with integrated physical layer

interface for 10BASE-T and 100BASE-TX

applications.

■ Support for PC99 wake on LAN

■ Provides 32-bit PCI bus master data transfer at

PCI clocks of 20-33 MHz

It was designed with advanced CMOS technology

to provide glueless 32-bit bus master interface for

PCI bus, boot ROM interface, CSMA/CD protocol

for fast ethernet, as well as the physical media

interface for 100BASE-TX of IEEE802.3u and

10BASE-T of IEEE802.3. The auto-negotiation

function is also supported for speed and duplex

detection.

■ Provides writable EEPROM/Boot rom interface

■ Provides independent transmission and

receiving FIFOs, each 2k bytes long

■ Supports big endian or little endian byte

ordering

■ ACPI and PCI compliant power management

functions offer significant power-savings

performance

The STE10/100A provides both half-duplex and

full-duplex operation, as well as support for full-

duplex flow control. It provides long FIFO buffers

for transmission and receiving, and early interrupt

mechanism to enhance performance. The

STE10/100A also supports ACPI and PCI

compliant power management function

■ Provides general purpose timers

■ 128-pin QFP package

February 2007

Rev 8

1/82

www.st.com

12 3 4 5 6 7...82

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