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DSPI56009FJ81 PDF预览

DSPI56009FJ81

更新时间: 2024-10-30 14:41:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟外围集成电路
页数 文件大小 规格书
83页 987K
描述
8-BIT, 81MHz, OTHER DSP, PQFP80, 14 X 14 MM, 2.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-80

DSPI56009FJ81 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:QFP包装说明:QFP, QFP80,.68SQ
针数:80Reach Compliance Code:unknown
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.57Is Samacsys:N
地址总线宽度:18桶式移位器:NO
位大小:24边界扫描:NO
最大时钟频率:81 MHz外部数据总线宽度:8
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PQFP-G80JESD-609代码:e0
长度:14 mm低功率模式:NO
端子数量:80最高工作温度:120 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP80,.68SQ
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not QualifiedRAM(字数):8960
座面最大高度:2.45 mm子类别:Digital Signal Processors
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

DSPI56009FJ81 数据手册

 浏览型号DSPI56009FJ81的Datasheet PDF文件第2页浏览型号DSPI56009FJ81的Datasheet PDF文件第3页浏览型号DSPI56009FJ81的Datasheet PDF文件第4页浏览型号DSPI56009FJ81的Datasheet PDF文件第5页浏览型号DSPI56009FJ81的Datasheet PDF文件第6页浏览型号DSPI56009FJ81的Datasheet PDF文件第7页 
MOTOROLA  
SEMICONDUCTOR TECHNICAL DATA  
Order this document by:  
DSP56009/D, Rev. 1  
DSP56009  
SYMPHONY AUDIO DSP FAMILY  
24-BIT DIGITAL SIGNAL PROCESSORS  
Motorola designed the Symphony™ family of high-performance, programmable Digital Signal  
Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic,  
Dolby AC-3 Surround, MPEG1 Layer 2, and Digital Theater Sound (DTS) processing. Software  
for these applications is licensed by Motorola for integration into products like audio/ video  
receivers, televisions, DVD applications, and automotive sound systems with such user-  
developed features as digital equalization and sound field processing. The DSP56009 is an MPU-  
style general purpose DSP, composed of an efficient 24-bit Digital Signal Processor core,  
program and data memories, various peripherals optimized for audio, and support circuitry. As  
illustrated in Figure 1, the DSP56000 core family compatible DSP is fed by program memory,  
two independent data RAMs and two data ROMs, a Serial Audio Interface (SAI), Serial Host  
Interface (SHI), External Memory Interface (EMI), dedicated I/ O lines, on-chip Phase Lock Loop  
(PLL), and On-Chip Emulation (OnCE ) port. The DSP56009 has more on-chip memory than  
the DSP56004 or DSP56007.  
ˇ
16-Bit Bus  
24-Bit Bus  
4
9
5
29  
General  
Purpose  
Input/  
Serial  
Serial  
External  
Audio  
Interface  
(SAI)  
Host  
Interface  
(SHI)  
Memory  
Interface  
(EMI)  
X Data  
Memory*  
Program  
Memory*  
Y Data  
Memory*  
Output  
PAB  
Address  
Generation  
Unit  
24-Bit  
DSP56000  
Core  
XAB  
YAB  
GDB  
PDB  
XDB  
YDB  
Internal  
Data  
Bus  
Switch  
TM  
OnCE Port  
Program  
Address  
Generator  
Program  
Decode  
Controller  
Data ALU  
24 × 24 + 56 56-Bit MAC  
Two 56-Bit Accumulators  
Interrupt  
Control  
Clock  
PLL  
Gen.  
Program Control Unit  
Refer to Table 1 for memory configurations.  
4
*
3
4
IRQA, IRQB, NMI, RESET  
AA0248  
Figure 1 DSP56009 Block Diagram  
©1996, 1997 MOTOROLA, INC.  
 

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