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DSPI

更新时间： 2024-01-24 12:40:02

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Serial Peripheral Interface - Master/Slave

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DSPI 数据手册

DSPI

Serial Peripheral Interface – Master/Slave

ver 2.07

made to write data to the serial shift register

O V E R V I E W

while a transfer is in progress. A multiple-

The DSPI is a fully configurable SPI mas-

ter/slave device, which allows user to config-

ure polarity and phase of serial clock signal

SCK.

master mode-fault detector automatically dis-

ables DSPI output drivers if more than one

SPI devices simultaneously attempts to be-

come bus master.

The DSPI allows the microcontroller to

communicate with serial peripheral devices. It

is also capable of interprocessor communica-

tions in a multi-master system. A serial clock

line (SCK) synchronizes shifting and sampling

of the information on the two independent se-

rial data lines. DSPI data are simultaneously

transmitted and received.

DSPI is fully customizable, which means it

is delivered in the exact configuration to meet

users’ requirements. There is no need to pay

extra for not used features and wasted silicon.

It includes fully automated testbench with

complete set of tests allowing easy package

validation at each stage of SoC design flow.

The DSPI is a technology independent de-

sign that can be implemented in a variety of

process technologies.

A P P L I C A T I O N S

● Embedded microprocessor boards

The DSPI system is flexible enough to in-

terface directly with numerous standard prod-

uct peripherals from several manufacturers.

The system can be configured as a master or

a slave device. Data rates as high as CLK/4.

Clock control logic allows a selection of clock

polarity and a choice of two fundamentally

different clocking protocols to accommodate

most available synchronous serial peripheral

devices. When the SPI is configured as a

master, software selects one of eight different

bit rates for the serial clock.

● Consumer and professional audio/video

● Home and automotive radio

● Digital multimeters

K E Y F E A T U R E S

● SPI Master

○

Master and Multi-master operations

8 SPI slave select lines

System error detection

The DSPI automatically drive selected by

SSCR (Slave Select Control Register) slave

select outputs (SS7O – SS0O), and address

SPI slave device to exchange serially shifted

data. Error-detection logic is included to sup-

port interprocessor communications. A write-

collision detector indicates when an attempt is

○ Mode fault error

○ Write collision error

○

Interrupt generation

Supports speeds up ¼ of system clock

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

12 3 4 5 6

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与DSPI相关器件

型号	品牌	获取价格	描述	数据表
DSPI56009FJ81	MOTOROLA	获取价格	8-BIT, 81MHz, OTHER DSP, PQFP80, 14 X 14 MM, 2.20 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-8
DSPIC	MICROCHIP	获取价格	16-bit Embedded Control Solutions PIC24 Microcontrollers dsPIC Digital Signal Controllers
DSPIC24H	MICROCHIP	获取价格	Flash Programming Specification
DSPIC30F	MICROCHIP	获取价格	dsPIC High-Performance 16-bit Digital Signal Controller Family Overview
DSPIC30F0010AT-20E/PF	MICROCHIP	获取价格	High-Performance, 16-Bit Digital Signal Controllers
DSPIC30F0010AT-20E/PT	MICROCHIP	获取价格	High-Performance, 16-Bit Digital Signal Controllers
DSPIC30F0010AT-20E/S	MICROCHIP	获取价格	High-Performance, 16-Bit Digital Signal Controllers
DSPIC30F0010AT-20I/PF	MICROCHIP	获取价格	High-Performance, 16-Bit Digital Signal Controllers
DSPIC30F0010AT-20I/PT	MICROCHIP	获取价格	High-Performance, 16-Bit Digital Signal Controllers
DSPIC30F0010AT-20I/S	MICROCHIP	获取价格	High-Performance, 16-Bit Digital Signal Controllers

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