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DSP96002FE40

更新时间: 2024-11-04 22:11:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 微控制器和处理器外围集成电路数字信号处理器装置时钟
页数 文件大小 规格书
111页 714K
描述
32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT PROCESSOR

DSP96002FE40 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:FQFP, QFP240,1.3SQ,20
针数:240Reach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.49地址总线宽度:32
桶式移位器:NO位大小:32
边界扫描:NO最大时钟频率:40 MHz
外部数据总线宽度:32格式:FLOATING POINT
集成缓存:NO内部总线架构:MULTIPLE
JESD-30 代码:S-CQFP-G240JESD-609代码:e0
长度:31.305 mm低功率模式:YES
DMA 通道数量:2外部中断装置数量:3
串行 I/O 数:端子数量:240
计时器数量:2片上数据RAM宽度:32
片上程序ROM宽度:最高工作温度:100 °C
最低工作温度:-40 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:FQFP封装等效代码:QFP240,1.3SQ,20
封装形状:SQUARE封装形式:FLATPACK, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not QualifiedRAM(字数):512
座面最大高度:4.15 mm子类别:Digital Signal Processors
最大压摆率:400 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:YES技术:HCMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:31.305 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

DSP96002FE40 数据手册

 浏览型号DSP96002FE40的Datasheet PDF文件第2页浏览型号DSP96002FE40的Datasheet PDF文件第3页浏览型号DSP96002FE40的Datasheet PDF文件第4页浏览型号DSP96002FE40的Datasheet PDF文件第5页浏览型号DSP96002FE40的Datasheet PDF文件第6页浏览型号DSP96002FE40的Datasheet PDF文件第7页 
Freescale Semiconductor, Inc.  
MOTOROLA  
Order this document by:  
DSP96002/D, Rev. 2  
SEMICONDUCTOR TECHNICAL DATA  
DSP96002  
32-BIT GENERAL PURPOSE FLOATING-POINT DUAL-PORT  
PROCESSOR  
The DSP96002 is designed to support intensive graphic image and numeric processing. It is  
a dual-port, low-power, general purpose floating-point processor. The DSP includes 1024  
words of data RAM (equally divided into X data and Y data memory), 1024 words of full-  
speed on-chip Program RAM, two data ROMs, a dual-channel Direct Memory Access (DMA)  
controller, special on-chip bootstrap hardware, and On-Chip Emulation (OnCE™) debug  
circuitry. The Central Processing Unit (CPU) consists of three 32-bit execution units  
operating in parallel. The DSP96002 has two identical memory expansion ports with control  
lines to facilitate interfacing SRAMs, DRAMs (operating in their fast access modes), and  
Video RAMs (VRAMs). Each port can be configured as a Host Interface (HI), which  
facilitates easy interface with other processors for multiprocessor applications. Linear arrays  
of DSP96002s can be implemented without glue logic. The MPU-style programming model  
and instruction set allow straightforward generation of efficient, compact code. The high  
speed of the DSP96002 makes it well-suited for high bandwidth and numerically intensive  
applications that require floating-point processing and access to large memory subsystems.  
Control  
18  
Control  
18  
Address  
Generation  
Unit (AGU)  
Bus  
Control  
Bus  
Control  
*
*
*
Address  
32  
YAB  
XAB  
PAB  
Address  
32  
External  
Address  
Switch  
External  
Address  
Switch  
Program  
*
*
*
X Data  
Memory  
512 × 32  
Y Data  
Memory  
512 × 32  
RAM  
4
Dual Channel  
DMA  
Controller  
Memory  
4
1024 × 32  
RAM and  
64 × 32  
Bootstrap  
ROM  
Instruction  
Cache  
RAM  
32-bit  
Host  
Interface  
32-bit  
Host  
Interface  
Internal  
Switch And Bit  
Manipulation  
Unit  
512 × 32† 512 × 32†  
ROM  
ROM  
Timer  
Timer  
DDB  
YDB  
XDB  
PDB  
GDB  
External  
Data  
Bus  
External  
Data  
Bus  
32  
Data  
32  
Data  
Switch  
Switch  
OnCE  
Debug  
Controller  
Clock  
Generator  
Program  
Decode  
Controller  
Program  
Address  
Generator  
Program  
Interrupt  
Controller  
Data ALU  
• IEEE Floating Point  
• 32 × 32 Integer ALU  
Program Controller  
4
MODC/IRQC  
MODB/IRQB  
MODA/IRQA  
CLK  
32-bit Buses  
Dual Access (DMA/Core)  
1024 × 32 Virtual Locations  
Serial Debug  
Port  
*
RESET  
AA0306  
Figure 1 Block Diagram  
For More Information On This Product,  
Go to: www.freescale.com  
©1996 MOTOROLA, INC.  

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