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DSP56ADC16S

更新时间： 2024-01-16 05:27:33
品牌 Logo 应用领域
其他 - ETC 转换器
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27页 297K
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DSP56ADC16S 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP20,.3Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.79Is Samacsys：N
最大模拟输入电压：2 V转换器类型：ADC, DELTA-SIGMA
JESD-30 代码：R-CDIP-T20JESD-609代码：e0
长度：24.515 mm模拟输入通道数量：1
位数：16功能数量：1
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出位码：2'S COMPLEMENT BINARY
输出格式：SERIAL封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified采样速率：0.4 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：5.08 mm
子类别：Analog to Digital Converters标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

DSP56ADC16S 数据手册

 浏览型号DSP56ADC16S的Datasheet PDF文件第2页浏览型号DSP56ADC16S的Datasheet PDF文件第3页浏览型号DSP56ADC16S的Datasheet PDF文件第4页浏览型号DSP56ADC16S的Datasheet PDF文件第5页浏览型号DSP56ADC16S的Datasheet PDF文件第6页浏览型号DSP56ADC16S的Datasheet PDF文件第7页 
Order this data sheet  
by DSP56ADC16/D  
MOTOROLA  
SEMICONDUCTOR  
TECHNICAL DATA  
DSP56ADC16  
Technical Information  
Available in a 20 pin  
CERDIP package  
DSP56ADC16  
16-bit Sigma-Delta Analog-to-Digital Converter  
The DSP56ADC16 is a single chip, linear, 16-bit oversampling analog-to-digital (A/D) converter, providing output  
sample rates up to 100 KHz. Third order noise shaping sigma-delta technology is employed utilizing 64 times  
oversampling which yields 96 dB dynamic range and 90 dB signal-to-noise ratio for the signal bandwidths from  
0 to 45.5 KHz with an in-band ripple of less than 0.001 dB. The DSP56ADC16 is an ideal choice for high perfor-  
mance digital audio systems, such as digital audio disks, tapes, and processors as well as voice-bandwidth com-  
munication and control applications. It does not require anti-aliasing filters and sample-and-hold circuitry  
because they are an inherent part of the sigma-delta technology. Due to the scalable design principles, the ef-  
fective output sampling rate can be adjusted from 8 KHz to 100 KHz without losing specified characteristics. The  
DSP56ADC16 can easily be interfaced to the DSP56001/2 or other host processors using its flexible serial inter-  
face. An output is also provided before the final FIR decimation filter for applications requiring higher speed, low-  
er group delay, and only 12-bit accuracy for AC levels. The DSP56ADC16 can also be used with an input  
multiplexer at a minimum output sampling interval of 15 µs in the comb filter output mode.  
DSP56ADC16 Key Features  
• 16-Bit Output Resolution (96 dB Typical Dynamic Range) at 100 KHz from the FIR Filter  
• 12-Bit Output Resolution (72 dB Typical Dynamic Range) at 400 KHz from the Comb Filter  
• 90 dB Signal-to-Noise Ratio (SNR)  
• In-Band Ripple: < 0.001 dB  
• Adjustable Output Sampling Rates:8 KHz to 100 KHz (FIR FIlter)  
32 KHz to 400 KHz (Comb Filter)  
• Maximum Input Sample Rate: 6.4 MHz  
• Maximum Internal Clock Rate:12.8 MHz  
• Single +5 V ±10% Supply  
• On-chip voltage reference  
• 3.5 Volt p-p full-scale differential inputs  
• Typical Power consumption: 300 mW at 100 KHz sampling rate  
• 20-Pin CERDIP Package  
• Single Chip  
• Linear Phase Analog Front End and Internal Digital Filters  
• Simple Serial Interface to Host Microprocessors  
• No-glue Interface to DSP5600x/DSP561xx and Most Other General Purpose DSPs  
This document contains information on a new product. Specifications and information herein are subject to change without notice.  
MOTOROLA  
MOTOROLA INC., 1992  
December 7, 1992  
1234567...27

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