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DSP56374PB/D PDF预览

DSP56374PB/D

更新时间: 2024-02-02 00:32:32
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
128页 1510K
描述
high density CMOS device with 3.3 V inputs and outputs

DSP56374PB/D 技术参数

是否Rohs认证: 符合生命周期:Transferred
Reach Compliance Code:unknown风险等级:5.84
位大小:24格式:FIXED POINT
JESD-30 代码:S-PQFP-G80端子数量:80
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP80,.64SQ封装形状:SQUARE
封装形式:FLATPACK电源:3.3 V
认证状态:Not QualifiedRAM(字数):6144
子类别:Digital Signal Processors最大压摆率:100 mA
标称供电电压:3.3 V表面贴装:YES
技术:CMOS端子形式:GULL WING
端子节距:0.635 mm端子位置:QUAD

DSP56374PB/D 数据手册

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DSP56374  
Rev. 1, 11/2004  
Freescale Semiconductor  
Technical Data  
Table of Contents  
Section  
Overview  
Page  
1 Features........................................2  
2 Documentation..............................4  
3 Signal Groupings ..........................4  
4 Maximum Ratings .......................24  
5 Power Requirements...................25  
6 Thermal Characteristics..............26  
7 DC Electrical Characteristics ......26  
8 AC Electrical Characteristics.......27  
9 Internal Clocks............................27  
10 External Clock Operation..........29  
The DSP56374 is a high density CMOS device with 3.3 V inputs and outputs.  
NOTE  
This document contains information on a new product.  
Specifications and information herein are subject to  
change without notice.  
Finalized specifications may be published after further characterization and device  
qualifications are completed.  
The DSP56374 supports digital audio applications requiring sound field processing,  
acoustic equalization, and other digital audio algorithms. The DSP56374 uses the high  
performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital  
signal processors (DSPs) combined with the audio signal processing capability of the  
Freescale Semiconductor, Inc. (formerly Motorola) Symphony™ DSP family, as shown in  
Figure 1. Significant architectural enhancements include a barrel shifter, 24-bit addressing,  
and direct memory access (DMA). The DSP56374 offers 150 million instructions per second  
(MIPS) using an internal 150 MHz clock.  
11 Reset, Stop, Mode Select, and  
Interrupt Timing...........................30  
12 Serial Host Interface SPI Protocol  
Timing..........................................34  
13 Serial Host Interface (SHI) I2C  
Protocol Timing ...........................40  
14 Programming the Serial Clock ..42  
Data Sheet Conventions  
This data sheet uses the following conventions:  
15 Enhanced Serial Audio Interface  
Timing..........................................43  
16 Timer Timing.............................48  
17 GPIO Timing .............................48  
18 JTAG Timing .............................50  
19 Watchdog Timer Timing............52  
Appendix A Package Information. 53  
Appendix B IBIS Model.................63  
OVERBAR Used to indicate a signal that is active when pulled low (For  
example, the RESET pin is active when low.)  
“asserted” Means that a high true (active high) signal is high or that a low true  
(active low) signal is low  
“deasserted” Means that a high true (active high) signal is low or that a low true  
(active low) signal is high  
Examples:  
Signal/  
Symbol  
Logic State  
Signal State  
Voltage*  
PIN  
PIN  
PIN  
PIN  
True  
False  
True  
Asserted  
Deasserted  
Asserted  
VIL / VOL  
VIH / VOH  
VIH / VOH  
VIL / VOL  
False  
Deasserted  
Note: *Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.  
© Freescale Semiconductor, Inc., 2004. All rights reserved.  
PRELIMINARY  

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