Datasheet > DSP56374FS

DSP56374FS

更新时间： 2024-09-30 23:49:15

品牌	Logo	应用领域
其他 - ETC		数字信号处理器
页数	文件大小	规格书
2页	83K
描述
DSP56374FS 24-Bit Audio Digital Signal Processor

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DSP56374FS 数据手册

24-Bit Audio Digital

Signal Processor

Overview

DSP56374 Features

On-chip Memory

Configuration

> 6Kx24 Bit Y-Data RAM and

4Kx24 Bit Y-Data ROM.

The DSP56374 is designed to support a

DSP Modular Chassis

multitude of digital signal processing applications

requiring a lot of horsepower in a small package.

While the DSP56374 is designed with flexibility

and thus is versatile in the types of applications it

can support, it does include a powerful set of

audio features, including various built-in audio

peripherals and embedded software designed to

meet the needs of both consumer and

automotive audio applications. The DSP56374

provides a wealth of audio processing functions

including an operating system, various

equalization algorithms, compression, signal

generator, tone control, fade/balance, level

meter/spectrum analyzer, and many more. The

DSP56374 also supports various matrix

> 1.25 V core with a 3.3 V peripheral I/O.

> 6Kx24 Bit X-Data RAM and

4Kx24 Bit X-Data ROM.

> 150 Million Instructions Per Second (MIPS)

with a 150 MHz clock at an internal logic

supply (QVDDL) of 1.25 V (0°C to 70°C for

consumer-grade devices;

> 6Kx24 Bit Program RAM.

> Various memory switches are

available. See memory table

below.

-40°C to 85°C for automotive-grade

devices).

> Object Code Compatible with the 56K core.

> 20Kx24 Bit Program and

Bootstrap ROM including a

PROM patching mechanism

> Data ALU with a 24 x 24 bit multiplier-

accumulator and a 56-bit barrel shifter.

16-bit arithmetic support.

> Program Control with position independent

code support and instruction

cache support.

decoders and sound field processing algorithms.

> Six-channel DMA controller.

The DSP56374 uses the high performance,

single-clock-per-cycle DSP56300 core family of

programmable CMOS digital signal processors

(DSPs) combined with the audio signal

processing capability of the Motorola

Symphony™ DSP family. This design provides a

two-fold performance increase over Motorola’s

popular DSP56000 core family of DSPs while

retaining code compatibility.

> Low jitter, PLL based clocking with a wide

range of frequency multiplications

(1 to 1024), predivider factors (1 to 32) and

power saving clock divider (2i: i=0

to 7). Reduces clock noise.

> Internal address tracing support and OnCE

for Hardware/Software debugging.

> JTAG port.

Significant architectural enhancements include a

barrel shifter, 24-bit addressing, patch module,

and direct memory access (DMA). The

DSP56374 is available in either a 52-pin or 80-

pin TQFP at 150 million instructions per second

(MIPS) using an internal 150 MHz clock at

1.25 V.

> Very low-power CMOS design, fully static

design with operating frequencies down to

DC.

> STOP and WAIT low-power standby modes.

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与DSP56374FS相关器件

型号	品牌	获取价格	描述	数据表
DSP56374PB	MOTOROLA	获取价格	high density CMOS device with 3.3 V inputs and outputs
DSP56374PB/D	MOTOROLA	获取价格	high density CMOS device with 3.3 V inputs and outputs
DSP56374PB/D	FREESCALE	获取价格	a high-density CMOS device
DSP56374UG	ETC	获取价格	DSP56374UG 24-Bit Digital Signal User Guide
DSP56374UM	MOTOROLA	获取价格	high density CMOS device with 3.3 V inputs and outputs
DSP56374UM/D	MOTOROLA	获取价格	high density CMOS device with 3.3 V inputs and outputs
DSP56374UM/D	FREESCALE	获取价格	a high-density CMOS device
DSP56600	FREESCALE	获取价格	Implementing Viterbi Decoders Using the VSL Instruction on DSP Families
DSP56600AD	FREESCALE	获取价格	16-BIT DIGITAL SIGNAL PROCESSOR
DSP56600FM	FREESCALE	获取价格	INTERGRATED CELLULAR BASEBAND PROCESSOR DEVELOPMENT IC

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