Datasheet > DSP56321RMAD

DSP56321RMAD

更新时间： 2024-09-27 23:49:15

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DSP56321 Reference Manual Addendum

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DSP56321RMAD 数据手册

Freescale Semiconductor, Inc.

Addendum

DSP56321RMAD/D

Rev. 4, 7/2003

DSP56321 Reference

Manual Addendum

CONTENTS

1 Introduction

Introduction...............1

Modified Signal

This document provides updated information for revision 0 of the DSP56321 Reference Manual

(DSP56321RM/D). The updates include the following:

Definitions.................1

Operating Mode

and Definition............2

Bus Control Register

(BCR) Layout and

• Modified signal definitions for some external bus control, HI08, ESSI, SCI, and timer signals

• New Operating Mode Register (OMR) layout and bit definitions

• New Bus Control Register (BCR) layout and bit definitions

• Updated GPIO signal names

Definition...................3

GPIO Signal Names..5

HDR Address.............5

SCI Receive Register

(SRX) Description .....5

UpdatedProgramming

Sheets.........................5

• Updated HDR address

• Updated SCI Receive Register (SRX) description

• Updated Programming sheets for the OMR, BCR, Address Attribute Registers (AAR[3–0]), and Timer

Registers (TLR, TCPR, TCR)

2 Modified Signal Definitions

Area to Change

Change Description

Figure 2-1, p. 2-2

•

Change HA10 to HA10

Table 2-8, pp. 2-5

and 2-6

•

Change the title of the third column to State During Reset, Stop, or Wait

Change the TA Signal Description to the following:

Transfer Acknowledge—If the DSP56321 is the bus master and there is no external

bus activity, or the DSP56321 is not the bus master, the TA input is ignored. The TA

input is a data transfer acknowledge (DTACK) function that can extend an external bus

cycle indefinitely. Any number of wait states (1, 2. . .infinity) can be added to the wait

states inserted by the bus control register (BCR) by keeping TA deasserted. In typical

operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion

of the bus cycle, and is deasserted before the next bus cycle. For correct operation, the

TAS bit must be set in the Operating Mode Register (OMR) to synchronize the TA signal

with the internal clock. The current bus cycle completes one clock period after TA is

deasserted. The number of wait states is determined by the TA input or by the BCR,

whichever is longer. The BCR sets the minimum number of wait states in external bus

‘cycles. In order to use the TA functionality, the BCR must be programmed to at least one

wait state. A zero wait state access cannot be extended by TA deassertion.

Change BR signal State During Reset, Stop, or Wait to:

What’s New?

Rev. 4 adds the

following update:

Section 6 updates the

listed address for the

Host Data Register

(HDR).

•

Reset: Output (deasserted)

State during Stop/Wait depends on BRH bit setting:

• BRH = 0: Output, deasserted

• BRH = 1: Maintains last state (that is, if asserted, remains asserted)

Change BB signal State During Reset, Stop, or Wait to Ignored input

For More Information On This Product,

Go to: www.freescale.com

12 3 4 5 6 7...12

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与DSP56321RMAD相关器件

型号	品牌	获取价格	描述	数据表
DSP56321TDS	ETC	获取价格	DSP56321T 24-Bit Digital Signal Processor
DSP56321TFC220	MOTOROLA	获取价格	24-BIT, 220MHz, OTHER DSP, PBGA196, PLASTIC, FLIP CHIP, BGA-196
DSP56321TFC220	NXP	获取价格	IC,DSP,24-BIT,CMOS,BGA,196PIN,PLASTIC
DSP56321TFC220D	MOTOROLA	获取价格	24-BIT, 220 MHz, OTHER DSP, PBGA196, 15 X 15 MM, 1 MM PITCH, MOLDED ARRAY PROCESS, BGA-196
DSP56321TFC240	MOTOROLA	获取价格	24-BIT, 240MHz, OTHER DSP, PBGA196, PLASTIC, FLIP CHIP, BGA-196
DSP56321TFC240	NXP	获取价格	IC,DSP,24-BIT,CMOS,BGA,196PIN,PLASTIC
DSP56321TFC240D	MOTOROLA	获取价格	Digital Signal Processor, 24-Ext Bit, 240MHz, CMOS, PBGA196, 15 X 15 MM, 1 MM PITCH, MOLDE
DSP56321TFC240D	NXP	获取价格	24-BIT, 240 MHz, OTHER DSP, PBGA196, 15 X 15 MM, 1 MM PITCH, MOLDED ARRAY PROCESS, BGA-196
DSP56321VF200	FREESCALE	获取价格	24-Bit Digital Signal Processor
DSP56321VF200R2	FREESCALE	获取价格	24-Bit Digital Signal Processor

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