Datasheet > 驱动程序和接口 > 线路驱动器或接收器> DS99R421

DS99R421

更新时间： 2024-10-01 03:13:51

品牌	Logo	应用领域
美国国家半导体 - NSC		转换器光电二极管时钟
页数	文件大小	规格书
18页	1015K
描述
5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Converter

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DS99R421 数据手册

January 8, 2008

DS99R421

5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single

Embedded Clock DC-Balanced LVDS Converter

General Description

Features

The DS99R421 converts a FPD-Link input with 4 non-DC

Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-

sampled low speed control bits into a single LVDS DC-bal-

anced serial stream with embedded clock information. This

single serial stream simplifies transferring the 24-bit bus over

a single differential pair of PCB traces and cable by eliminat-

ing the skew problems between the 3 parallel LVDS data

inputs and LVDS clock paths. It saves system cost by nar-

rowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB

layers, cable width, connector size, and pins.

5 MHz–43 MHz embedded clock & DC-Balanced data

■

transmission (21 total LVDS data bits plus 3 low speed

LVCMOS data bits)

User adjustable pre-emphasis driving ability through

external resistor on LVDS outputs and capable to drive up

to 10 meters shielded twisted-pair cable

■

Supports AC-coupling data transmission

■

100Ω Integrated termination resistor at LVDS input

Power-down control

■

Available @SPEED BIST to DS90UR124 to validate link

integrity

The DS99R421 incorporates a single serialized LVDS signal

on the high-speed I/O. Embedded clock LVDS provides a low

power and low noise environment for reliably transferring data

over a serial transmission path. By optimizing the converter

output edge rate for the operating frequency range EMI is fur-

ther reduced.

All LVCMOS inputs & control pins have internal pulldown

■

Schmitt trigger inputs on OS[2:0] to minimize metastable

conditions.

Outputs Tri-Stated through DEN

■

In addition the device features pre-emphasis to boost signals

over longer distances using lossy cables. Internal DC bal-

anced encoding is used to support AC-Coupled intercon-

nects.

On-chip filters for PLLs

Power supply range 3.3V ± 10%

Automotive temperature range −40°C to +105°C

Greater than 8kV ESD Tolerance

Meets ISO 10605 ESD and AEC-Q100 compliance

Block Diagram

30011301

FIGURE 1. Block Diagram

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

300113

www.national.com

12 3 4 5 6 7...18

中文翻译

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与DS99R421相关器件

型号	品牌	获取价格	描述	数据表
DS99R421_08	NSC	获取价格	5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Conver
DS99R421ISQ	NSC	获取价格	5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Conver
DS99R421ISQX	NSC	获取价格	5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Conver
DS99R421-Q1	TI	获取价格	5-43MHz FPD 链接 LVDS（3 数据 + 1 时钟）至 FPD-Link II
DS99R421QSQ	NSC	获取价格	5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Conver
DS99R421QSQ/NOPB	TI	获取价格	5-43MHz FPD 链接 LVDS（3 数据 + 1 时钟）至 FPD-Link II
DS99R421QSQX	NSC	获取价格	5-43 MHz FPD-Link LVDS (3 Data + 1 Clock) to Single Embedded Clock DC-Balanced LVDS Conver
DS99R421QSQX/NOPB	TI	获取价格	5-43MHz FPD 链接 LVDS（3 数据 + 1 时钟）至 FPD-Link II
DSA/DSO90254A	KEYSIGHT	获取价格	Infiniium 90000 Series Oscilloscopes
DSA/DSO90404A	KEYSIGHT	获取价格	Infiniium 90000 Series Oscilloscopes

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