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DS96F175MJ PDF预览

DS96F175MJ

更新时间： 2024-02-08 09:22:48
品牌 Logo 应用领域
美国国家半导体 - NSC 接口集成电路
页数 文件大小 规格书
10页 236K
描述
IC QUAD LINE RECEIVER, CDIP16, CERDIP-16, Line Driver or Receiver

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中文翻译

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DS96F175MJ 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：DIP, DIP16,.3Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.19输入特性：DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型：LINE RECEIVER接口标准：EIA-422-A; EIA-423-A; EIA-485
JESD-30 代码：R-GDIP-T16JESD-609代码：e0
长度：19.43 mm功能数量：4
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
最大输出低电流：0.016 A输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
认证状态：Not Qualified最大接收延迟：30 ns
接收器位数：4座面最大高度：5.08 mm
子类别：Line Driver or Receivers最大压摆率：50 mA
标称供电电压：5 V表面贴装：NO
技术：BIPOLAR温度等级：MILITARY
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

DS96F175MJ 数据手册

 浏览型号DS96F175MJ的Datasheet PDF文件第2页浏览型号DS96F175MJ的Datasheet PDF文件第3页浏览型号DS96F175MJ的Datasheet PDF文件第4页浏览型号DS96F175MJ的Datasheet PDF文件第5页浏览型号DS96F175MJ的Datasheet PDF文件第6页浏览型号DS96F175MJ的Datasheet PDF文件第7页 
July 2000  
DS96F173M/DS96F175C/DS96F175M  
EIA-485/EIA-422 Quad Differential Receivers  
General Description  
Features  
n Meets EIA-485, EIA-422A, EIA-423A standards  
n Designed for multipoint bus applications  
n TRI-STATE outputs  
The DS96F173 and the DS96F175 are high speed quad dif-  
ferential line receivers designed to meet the EIA-485 stan-  
dard. The DS96F173 and the DS96F175 offer improved per-  
formance due to the use of L-FAST bipolar technology. The  
use of LFAST technology allows the DS96F173 and  
DS96F175 to operate at higher speeds while minimizing  
power consumption.  
n Common mode input voltage range: −7V to +12V  
n Operates from single +5.0V supply  
n Reduced power consumption (ICC = 50 mA max)  
n Input sensitivity of 200 mV over common mode range  
n Input hysteresis of 50 mV typical  
n High input impedance  
±
The DS96F173 and the DS96F175 have TRI-STATE® out-  
puts and are optimized for balanced multipoint data bus  
transmission at rates up to 15 Mbps. The receivers feature  
high input impedance, input hysteresis for increased noise  
immunity, and input sensitivity of 200 mV over a common  
mode input voltage range of −7V to +12V. The receivers are  
therefore suitable for multipoint applications in noisy environ-  
ments. The DS96F173 features an active high and active  
low Enable, common to all four receivers. The DS96F175  
features separate active high Enables for each receiver pair.  
n Military temperature range available  
n Qualified for MIL STD 883C  
n Available to standard military drawings (SMD)  
n Available in DIP(J), LCC(E), and FlatPak (W) packages  
n DS96F173 and DS96F175 are lead and function  
compatible with SN75173/175 or the  
AM26LS32/MC3486  
Logic Diagrams  
Function Tables  
(Each Receiver) DS96F173  
Differential Inputs  
Enable  
Output  
A–B  
E
E
X
L
Y
H
H
L
VID ≥ 0.2V  
H
X
H
X
L
VID ≤ −0.2V  
X
L
DS009627-10  
L
DS96F175  
X
X
X
H
Z
Z
X
H = High Level  
L = Low Level  
Z = High Impedance (off)  
X = Don’t Care  
(Each Receiver) DS96F175  
Differential Inputs  
Enable  
Output  
DS009627-11  
A–B  
E
H
H
L
Y
H
L
VID ≥ 0.2V  
VID ≤ −0.2V  
X
Z
TRI-STATE® is a registered trademark of National Semiconductor Corporation.  
© 2000 National Semiconductor Corporation  
DS009627  
www.national.com  
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